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ORCIDYves Blaquière
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2020 – today
- 2024
[c40]Amirhossein Moshrefi, Yves Blaquière, Frederic Nabki:
A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier. ISCAS 2024: 1-5- [c39]Allan Riboullet, Frédéric Nabki, Yves Blaquière, Glenn E. R. Cowan:
Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches. ISCAS 2024: 1-5 - 2023
- [j16]Hachem Bensalem
, Yves Blaquière, Yvon Savaria:
An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1144-1148 (2023) - [c38]Hamid Sadrimanesh, Yves Blaquière, Frederic Nabki:
Toward 2.5D Structures for Multi-Channel MEMS Acoustic-Based Digital Isolators using Through Silicon Openings. NEWCAS 2023: 1-5 - [c37]Abdurrashid Hassan Shuaibu, Yves Blaquière, Frédéric Nabki:
Toward a Polysilicon-Based Electrostatically Actuated DC MEMS Switch. NEWCAS 2023: 1-4 - 2022
- [c36]Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan:
Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications. NEWCAS 2022: 183-187 - [c35]Van Ha Nguyen, Nueraimaiti Aimaier, Gabriel Nobert, Tan Pham, Nicolas G. Constantin, Yves Blaquière, Glenn E. R. Cowan:
A Reconfigurable Power System-in-Package Module using GaN HEMTs and IC Bare Dies on LTCC Substrate: Design - Implementation - Experiment and Future Directions. NEWCAS 2022: 188-192 - [c34]Van Ha Nguyen, Xuan-Dien Do, Yves Blaquière, Glenn E. R. Cowan:
A 3.3 V 0.1-1 A Hybrid Buck-Boost Converter with 85-97 % Power Efficiency Range Highly-Suited for Battery-Powered Devices using Low-Profile High-DCR Inductor. NEWCAS 2022: 303-307 - [c33]Abdurrashid Hassan Shuaibu, Frédéric Nabki, Yves Blaquière:
A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience. NEWCAS 2022: 317-321 - 2021
- [j15]Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan:
A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1625-1629 (2021) - [j14]Safa Berrima, Yves Blaquière, Yvon Savaria:
Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Trans. Instrum. Meas. 70: 1-10 (2021) - [c32]Nueraimaiti Aimaier, Nam Ly, Gabriel Nobert, Yves Blaquière, Nicolas G. Constantin, Glenn E. R. Cowan:
SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit. ISCAS 2021: 1-5 - [c31]Hachem Bensalem, Yves Blaquière, Yvon Savaria:
Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. ISCAS 2021: 1-5 - [c30]Van Ha Nguyen, Abdul Hafiz Alameh, Nam Ly, Yves Blaquière, Glenn E. R. Cowan:
A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller. ISCAS 2021: 1-5 - [c29]Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan:
Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator. ISCAS 2021: 1-5 - [c28]Gabriel Nobert, Abdul Hafiz Alameh, Nam Ly, Nicolas G. Constantin, Yves Blaquière:
Towards an LTCC SiP for Control System in Safety-Critical Applications. ISCAS 2021: 1-5 - 2020
- [j13]Hachem Bensalem, Yves Blaquière, Yvon Savaria:
In-FPGA Instrumentation Framework for OpenCL-Based Designs. IEEE Access 8: 212979-212994 (2020) - [j12]Safa Berrima, Yves Blaquière, Yvon Savaria:
Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices Syst. 14(8): 1243-1252 (2020) - [c27]Nam Ly, Nueraimaiti Aimaier, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan, Nicolas G. Constantin:
A High Voltage Multi-Purpose On-the-fly Reconfigurable Half-Bridge Gate Driver for GaN HEMTs in 0.18-μm HV SOI CMOS Technology. NEWCAS 2020: 178-181
2010 – 2019
- 2019
- [j11]Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan:
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 304-315 (2019) - [c26]Hachem Bensalem, Yves Blaquière, Yvon Savaria:
Toward In-System Monitoring of OpenCL-Based Designs on FPGA. ISCAS 2019: 1-5 - 2018
- [j10]Safa Berrima, Yves Blaquière, Yvon Savaria:
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integr. 62: 159-169 (2018) - [j9]Etienne Lepercq, Yves Blaquière, Yvon Savaria:
A pattern-based routing algorithm for a novel electronic system prototyping platform. Integr. 62: 224-237 (2018) - [i2]Mostafa Darvishi, Yves Audet, Yves Blaquière:
Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA. CoRR abs/1807.11311 (2018) - 2017
- [c25]Safa Berrima, Yves Blaquière, Yvon Savaria:
A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. ISCAS 2017: 1-4 - [c24]Safa Berrima, Yves Blaquière, Yvon Savaria:
Sub-ps resolution programmable delays implemented in a Xilinx FPGA. MWSCAS 2017: 918-921 - 2016
- [j8]Wasim Hussain, Olivier Valorge, Yves Blaquière, Yvon Savaria:
A novel spatially configurable differential interface for an electronic system prototyping platform. Integr. 55: 129-137 (2016) - [j7]Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco:
Towards an efficient SEU effects emulation on SRAM-based FPGAs. Microelectron. Reliab. 66: 173-182 (2016) - [j6]Wasim Hussain, Hussein Fakhoury, Patricia Desgreys, Yves Blaquière, Yvon Savaria:
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 751-762 (2016) - [c23]Wasim Hussain, Yvon Savaria, Yves Blaquière:
A compact spatially configurable differential input stage for a field programmable interconnection network. ISCAS 2016: 313-316 - 2015
- [j5]Wasim Hussain, Yves Blaquière, Yvon Savaria:
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2465-2475 (2015) - [c22]Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco:
An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. EWDTS 2015: 1-4 - [c21]Anis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco:
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. IOLTS 2015: 36-39 - [c20]Gontran Sion, Yves Blaquière, Yvon Savaria:
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. IOLTS 2015: 83-88 - [i1]Mostafa Darvishi, Yves Audet, Yves Blaquière, Claude Thibeault:
Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. CoRR abs/1502.03057 (2015) - 2014
- [j4]Nicolas Laflamme-Mayer, Yves Blaquière, Yvon Savaria, Mohamad Sawan:
A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3135-3144 (2014) - [c19]Yves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria:
Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. ISCAS 2014: 2559-2562 - 2013
- [j3]Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, Mohamad Sawan:
Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2024-2033 (2013) - [c18]Mikael Guillemot, Yves Blaquière, Yvon Savaria:
Software rendering methods to display wafer scale integrated circuit dataset. CCECE 2013: 1-4 - [c17]Wasim Hussain, Yvon Savaria, Yves Blaquière:
An interface for the I2C protocol in the WaferBoard™. ISCAS 2013: 1492-1495 - [c16]Nicolas Laflamme-Mayer, Mohamad Sawan, Yves Blaquière:
A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. LASCAS 2013: 1-4 - [c15]Karim Baratli, Ahmed Lakhssassi, Yves Blaquière, Yvon Savaria:
A netlist pruning tool for an electronic system prototyping platform. NEWCAS 2013: 1-4 - 2012
- [c14]Omar Al-Terkawi Hasib, Walder Andre, Yves Blaquière, Yvon Savaria:
Propagating analog signals through a fully digital network on an electronic system prototyping platform. ISCAS 2012: 1983-1986 - [c13]Michel Sayde, Ahmed Lakhssassi, Mohammed Bougataya, Omar Terkawi, Yves Blaquière:
SoC systems thermal monitoring using embedded sensor cells unit. MWSCAS 2012: 1052-1055 - [c12]Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière:
A new approach for pin detection for an electronic system prototyping reconfigurable platform. RSP 2012: 122-127 - 2011
- [c11]Nicolas Laflamme-Mayer, Yves Blaquière, Mohamad Sawan:
A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems. ICECS 2011: 25-28 - [c10]Mohamed Badreddine, Yves Blaquière, Mounir Boukadoum:
Machine-learning framework for automatic netlist creation. ISCAS 2011: 2865-2868 - 2010
- [c9]Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula:
Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. ICECS 2010: 315-318 - [c8]Olivier Valorge, Yves Blaquière, Yvon Savaria:
A spatially reconfigurable fast differential interface for a wafer scale configurable platform. ICECS 2010: 1176-1179
2000 – 2009
- 2009
- [c7]Etienne Lepercq, Yves Blaquière, Richard Norman, Yvon Savaria:
Workflow for an Electronic Configurable Prototyping System. ISCAS 2009: 2005-2008 - 2008
- [c6]Olivier Valorge, Anh Tuan Nguyen, Yves Blaquière, Richard Norman, Yvon Savaria:
Digital signal propagation on a wafer-scale smart active programmable interconnect. ICECS 2008: 1059-1062 - [c5]Yan Basile-Bellavance, Etienne Lepercq, Yves Blaquière, Yvon Savaria:
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. ICECS 2008: 1159-1162 - 2007
- [c4]Yves Blaquière, Yvon Savaria, Jaouad El Fouladi:
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os. ICECS 2007: 42-45 - 2000
- [c3]Marc-André Cantin, Yves Blaquière, Yvon Savaria, Pierre Lavoie, Eric Granger:
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. ISCAS 2000: 141-144
1990 – 1999
- 1998
- [c2]Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria:
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. FCCM 1998: 304-305 - 1996
- [j2]Yves Blaquière, Michel R. Dagenais, Yvon Savaria:
Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 244-255 (1996) - 1995
- [c1]Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz:
Cost analysis of a new algorithmic-based soft-error tolerant architecture. DFT 1995: 189-197 - 1990
- [j1]Yves Blaquière, Jacob Davidson:
VHDL design of a priority interrupt controller and synchronizer for the MC68008. Microprocess. Microsystems 14(7): 474-478 (1990)
Coauthor Index
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last updated on 2024-07-17 20:33 CEST by the dblp team
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