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Nestoras Tzartzanis
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2010 – 2019
- 2010
- [j10]Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker:
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45(10): 2016-2029 (2010)
2000 – 2009
- 2009
- [j9]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3580-3589 (2009) - [c12]Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker:
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC 2009: 360-361 - 2007
- [j8]Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A Leakage Current Replica Keeper for Dynamic Circuits. IEEE J. Solid State Circuits 42(1): 48-55 (2007) - [j7]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42(12): 2726-2735 (2007) - [c11]Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC 2007: 224-598 - 2006
- [c10]Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A leakage current replica keeper for dynamic circuits. ISSCC 2006: 1755-1764 - [c9]Nestoras Tzartzanis, William W. Walker:
A Reversible Poly-Phase Distributed VCO. ISSCC 2006: 2452-2461 - 2005
- [j6]Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda:
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40(8): 1680-1687 (2005) - [j5]Nestoras Tzartzanis, William W. Walker:
Differential current-mode sensing for efficient on-chip global signaling. IEEE J. Solid State Circuits 40(11): 2141-2147 (2005) - [j4]Hisashige Ando, Nestoras Tzartzanis, William W. Walker:
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 865-868 (2005) - 2003
- [c8]Nestoras Tzartzanis, William W. Walker:
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. ICCD 2003: 107- - 2000
- [j3]William C. Athas, Nestoras Tzartzanis, Weihua Mao, Lena Peterson, Rajat Lal, Kisup Chong, Joong-Seok Moon, Lars J. Svensson, Michael Bolotski:
The design and implementation of a low-power clock-powered microprocessor. IEEE J. Solid State Circuits 35(11): 1561-1570 (2000)
1990 – 1999
- 1999
- [c7]Nestoras Tzartzanis, William C. Athas:
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. ARVLSI 1999: 137-153 - [c6]Nestoras Tzartzanis, William C. Athas:
Retractile clock-powered logic. ISLPED 1999: 18-23 - 1997
- [j2]William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson:
A low-power microprocessor based on resonant energy. IEEE J. Solid State Circuits 32(11): 1693-1701 (1997) - [c5]William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, Weichuan Liu:
AC-1: a clock-powered microprocessor. ISLPED 1997: 328-333 - 1996
- [c4]Nestoras Tzartzanis, William C. Athas:
Energy recovery for the design of high-speed, low-power static RAMs. ISLPED 1996: 55-60 - 1995
- [c3]William C. Athas, Nestoras Tzartzanis:
Energy recovery for low-power CMOS. ARVLSI 1995: 415-429 - [c2]Nestoras Tzartzanis, William C. Athas:
Design and analysis of a low-power energy-recovery adder. Great Lakes Symposium on VLSI 1995: 66-69 - 1994
- [j1]William C. Athas, Lars J. Svensson, Jefferey G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou:
Low-power digital systems based on adiabatic-switching principles. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 398-407 (1994) - 1991
- [c1]Manolis Katevenis, Nestoras Tzartzanis:
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. ASPLOS 1991: 15-27
Coauthor Index
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