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Journal Articles
- 2019
[j2]Ioannis Seitanidis, Giorgos Dimitrakopoulos
, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing-Driven and Placement-Aware Multibit Register Composition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1501-1514 (2019)- 2015
- [j1]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 589-602 (2015)
Conference and Workshop Papers
- 2017
- [c4]Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. DAC 2017: 56:1-56:6 - 2015
- [c3]Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet:
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. ACM Great Lakes Symposium on VLSI 2015: 87-90 - 2014
- [c2]Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD 2014: 69-76 - 1991
- [c1]J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, Laurent Masse-Navette:
A Customizable Neural Processor for Distributed Neural Network. VLSI 1991: 167-176
Coauthor Index
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