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ORCIDCheng Liu 0008
Person information
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
- affiliation (PhD 2016): University of Hong Kong, Department of Electrical and Electronic Engineering, Hong Kong
Other persons with the same name
- Cheng Liu — disambiguation page
- Cheng Liu 0001
![[0000-0002-3723-9424]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-3723-9424")
— Shantou University, Department of Computer Science, China (and 1 more) - Cheng Liu 0002 — Georgia Institute of Technology, Atlanta, GA, USA
- Cheng Liu 0003 — Kyushu University, Research Institute for Applied Mechanics, Fukuoka, Japan
- Cheng Liu 0004 — Stanford University, Department of Aeronautics and Astronautics, Stanford, CA, USA
- Cheng Liu 0005 — University of Science and Technology of China, School of Earth and Space Sciences, Hefei, China
- Cheng Liu 0006 — Shenzhen Institute of Building Research Co., Shenzhen, China (and 1 more)
- Cheng Liu 0007 — Chinese Academy of Sciences, National Space Science Center, Beijing, China (and 1 more)
- Cheng Liu 0009 — Harbin Institute of Technology, School of Electrical Engineering and Automation, Harbin, China
- Cheng Liu 0010 — Dalian Maritime University, College of Navigation, Dalian, China (and 1 more)
- Cheng Liu 0011 — Guizhou University, College of Computer Science and Technology, Guiyang, China
- Cheng Liu 0012 — Beijing Jiaotong University, Institute of Information Science, Beijing, China
- Cheng Liu 0013 — Xi'an Polytechnic University, School of Electronics and Information, Xi'an, China
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2020 – today
- 2024
[j29]Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li:
PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1246-1259 (2024)- [j28]Mingkai Chen, Cheng Liu, Shengwen Liang, Lei He, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li:
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1781-1793 (2024) - [j27]Yintao He, Bing Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2635-2646 (2024) - [j26]YaJuan Hui, Qingzhen Li, Cheng Liu, Deming Zhang, Xiangshui Miao:
Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2309-2313 (2024) - [j25]Long Cheng, Yue Wang, Feng Cheng, Cheng Liu, Zhiming Zhao, Ying Wang:
A Deep Reinforcement Learning-Based Preemptive Approach for Cost-Aware Cloud Job Scheduling. IEEE Trans. Sustain. Comput. 9(3): 422-432 (2024) - [j24]YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, Xiangshui Miao:
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 497-504 (2024) - [j23]Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li:
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1325-1335 (2024) - [i23]Qing Zhang, Cheng Liu, Siting Liu, Yajuan Hui, Huawei Li, Xiaowei Li:
ApproxPilot: A GNN-based Accelerator Approximation Framework. CoRR abs/2407.11324 (2024) - [i22]Fangfa Fu, Wenyu Zhang, Zesong Jiang, Zhiyu Zhu, Guoyu Li, Bing Yang, Cheng Liu, Liyi Xiao, Jinxiang Wang, Huawei Li, Xiaowei Li:
SigDLA: A Deep Learning Accelerator Extension for Signal Processing. CoRR abs/2407.12565 (2024) - [i21]Xinmiao Zhang, Zheng Feng, Shengwen Liang, Xinyu Chen, Cheng Liu, Huawei Li, Xiaowei Li:
Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. CoRR abs/2407.12575 (2024) - [i20]Zesong Jiang, Qing Zhang, Cheng Liu, Huawei Li, Xiaowei Li:
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA. CoRR abs/2407.12576 (2024) - 2023
- [b1]Xiaowei Li, Guihai Yan, Cheng Liu:
Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design - A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach. Springer 2023, ISBN 978-981-19-8550-8, pp. 1-304 - [j22]Yuquan He, Long Zhang, Cheng Liu, Lei Zhang, Ying Wang:
S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms. IEEE Robotics Autom. Lett. 8(3): 1826-1833 (2023) - [j21]Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li:
On-Line Fault Protection for ReRAM-Based Neural Networks. IEEE Trans. Computers 72(2): 423-437 (2023) - [j20]Hao Lv, Bing Li, Lei Zhang, Cheng Liu, Ying Wang:
Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1588-1596 (2023) - [j19]Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang:
Network Pruning for Bit-Serial Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1597-1609 (2023) - [j18]Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li:
Statistical Modeling of Soft Error Influence on Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4152-4163 (2023) - [j17]Weiwei Chen, Ying Wang, Ying Xu, Chengsi Gao, Cheng Liu, Lei Zhang:
A Framework for Neural Network Architecture and Compile Co-optimization. ACM Trans. Embed. Comput. Syst. 22(1): 5:1-5:24 (2023) - [j16]Cheng Chu, Cheng Liu, Dawen Xu, Ying Wang, Tao Luo, Huawei Li, Xiaowei Li:
Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. ACM Trans. Design Autom. Electr. Syst. 28(4): 67:1-67:23 (2023) - [j15]Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1763-1773 (2023) - [j14]Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Soft Error Reliability Analysis of Vision Transformers. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2126-2136 (2023) - [c38]Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang:
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. DATE 2023: 1-6 - [c37]Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. ICCAD 2023: 1-9 - [c36]Neo Wei Ming, Zhehui Wang, Cheng Liu, Rick Siow Mong Goh, Tao Luo:
MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-Linear Functions. ICLR 2023 - [i19]Hao Lv, Bing Li, Lei Zhang, Cheng Liu, Ying Wang:
Variation Enhanced Attacks Against RRAM-based Neuromorphic Computing System. CoRR abs/2302.09902 (2023) - [i18]Xinghua Xue, Cheng Liu, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Reliability Analysis of Vision Transformers. CoRR abs/2302.10468 (2023) - [i17]Xinghua Xue, Cheng Liu, Haitong Huang, Ying Wang, Bing Yang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. CoRR abs/2302.10469 (2023) - [i16]Haitong Huang, Cheng Liu, Xinghua Xue, Ying Wang, Huawei Li, Xiaowei Li:
MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. CoRR abs/2306.11758 (2023) - [i15]Haitong Huang, Cheng Liu:
Deep Learning Accelerator in Loop Reliability Evaluation for Autonomous Driving. CoRR abs/2306.11759 (2023) - [i14]Xinghua Xue, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Tao Luo, Lei Zhang, Huawei Li, Xiaowei Li:
Exploring Winograd Convolution for Cost-effective Neural Network Fault Tolerance. CoRR abs/2308.08230 (2023) - [i13]Erjing Luo, Haitong Huang, Cheng Liu, Guoyu Li, Bing Yang, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. CoRR abs/2308.11334 (2023) - [i12]Qing Zhang, Cheng Liu, Bo Liu, Haitong Huang, Ying Wang, Huawei Li, Xiaowei Li:
Cross-Layer Optimization for Fault-Tolerant Deep Learning. CoRR abs/2312.13754 (2023) - 2022
- [j13]Benjamin Chen Ming Choong, Tao Luo, Cheng Liu, Bingsheng He, Wei Zhang, Joey Tianyi Zhou:
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems. J. Syst. Archit. 128: 102507 (2022) - [j12]Cheng Liu, Cheng Chu, Dawen Xu, Ying Wang, Qianlong Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3400-3413 (2022) - [j11]Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 418-431 (2022) - [c35]Yuquan He, Songyun Qu, Gangliang Lin, Cheng Liu, Lei Zhang, Ying Wang:
Processing-in-SRAM acceleration for ultra-low power visual 3D perception. DAC 2022: 295-300 - [c34]Xinghua Xue, Haitong Huang, Cheng Liu, Tao Luo, Lei Zhang, Ying Wang:
Winograd convolution: a perspective from fault tolerance. DAC 2022: 853-858 - [c33]Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li:
VStore: in-storage graph based vector search accelerator. DAC 2022: 997-1002 - [c32]Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. DATE 2022: 1035-1040 - [c31]Lei Dai, Ying Wang, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li:
Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. ICCD 2022: 42-49 - [c30]Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li:
Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective. VTS 2022: 1-12 - [i11]Xinghua Xue, Haitong Huang, Cheng Liu, Ying Wang, Tao Luo, Lei Zhang:
Winograd Convolution: A Perspective from Fault Tolerance. CoRR abs/2202.08675 (2022) - [i10]Cheng Liu, Zhen Gao, Siting Liu, Xuefei Ning, Huawei Li, Xiaowei Li:
Fault-Tolerant Deep Learning: A Hierarchical Perspective. CoRR abs/2204.01942 (2022) - [i9]Haitong Huang, Xinghua Xue, Cheng Liu, Ying Wang, Tao Luo, Long Cheng, Huawei Li, Xiaowei Li:
Statistical Modeling of Soft Error Influence on Neural Networks. CoRR abs/2210.05876 (2022) - 2021
- [j10]Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li:
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. IEEE Trans. Computers 70(9): 1511-1525 (2021) - [j9]Long Cheng, Ying Wang, Qingzhi Liu, Dick H. J. Epema, Cheng Liu, Ying Mao, John Murphy:
Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers. IEEE Trans. Parallel Distributed Syst. 32(6): 1494-1510 (2021) - [j8]Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Shuang Zhao, Lei Zhang, Huaguo Liang, Huawei Li, Kwang-Ting Cheng:
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 472-484 (2021) - [j7]Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1955-1966 (2021) - [c29]Hao Lv, Bing Li, Ying Wang, Cheng Liu, Lei Zhang:
VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack. ASP-DAC 2021: 487-492 - [c28]Mengdi Wang, Ying Wang, Cheng Liu, Lei Zhang:
Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. DAC 2021: 49-54 - [c27]Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li:
GCiM: A Near-Data Processing Accelerator for Graph Construction. DAC 2021: 205-210 - [c26]Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. DAC 2021: 577-582 - [c25]Mengdi Wang, Bing Li, Ying Wang, Cheng Liu, Xiaohan Ma, Xiandong Zhao, Lei Zhang:
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. ACM Great Lakes Symposium on VLSI 2021: 1-8 - [c24]Yuquan He, Ying Wang, Cheng Liu, Lei Zhang:
PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices. ICRA 2021: 5567-5573 - [c23]Xiaohan Ma, Chang Si, Ying Wang, Cheng Liu, Lei Zhang:
NASA: Accelerating Neural Network Design with a NAS Processor. ISCA 2021: 790-803 - [c22]Weiwei Chen, Ying Wang, Gangliang Lin, Chengsi Gao, Cheng Liu, Lei Zhang:
CHaNAS: coordinated search for network architecture and scheduling policy. LCTES 2021: 42-53 - [c21]Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li:
GLIST: Towards In-Storage Graph Learning. USENIX ATC 2021: 225-238 - [i8]Dawen Xu, Qianlong Wang, Cheng Liu, Cheng Chu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
HyCA: A Hybrid Computing Architecture for Fault Tolerant Deep Learning. CoRR abs/2106.04772 (2021) - [i7]Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
Energy-Efficient Accelerator Design for Deformable Convolution Networks. CoRR abs/2107.02547 (2021) - [i6]Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors. CoRR abs/2107.03096 (2021) - [i5]Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li:
Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR abs/2108.05023 (2021) - 2020
- [j6]Dawen Xu, Cheng Liu, Ying Wang, Kaijie Tu, Bingsheng He, Lei Zhang:
Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach. IEEE Trans. Computers 69(8): 1172-1184 (2020) - [c20]Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng:
Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. ASAP 2020: 85-92 - [c19]Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang:
BitPruner: Network Pruning for Bit-serial Accelerators. DAC 2020: 1-6 - [c18]Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li:
CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. DATE 2020: 963-966 - [c17]Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang, Huawei Li:
Multi-task Scheduling for PIM-based Heterogeneous Computing System. ACM Great Lakes Symposium on VLSI 2020: 457-462 - [c16]Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. ICCAD 2020: 72:1-72:9 - [c15]Dawen Xu, Cheng Chu, Qianlong Wang, Cheng Liu, Ying Wang, Lei Zhang, Huaguo Liang, Kwang-Ting Cheng:
A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. ICCD 2020: 478-485 - [c14]Tao Luo, Wei Zhang, Bingsheng He, Cheng Liu, Douglas L. Maskell:
Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. ICDCS 2020: 1409-1414 - [c13]Xiandong Zhao, Ying Wang, Xuyi Cai, Cheng Liu, Lei Zhang:
Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware. ICLR 2020
2010 – 2019
- 2019
- [j5]Chuangyi Gui, Long Zheng, Bingsheng He, Cheng Liu, Xinyu Chen, Xiaofei Liao, Hai Jin:
A Survey on Graph Processing Accelerators: Challenges and Opportunities. J. Comput. Sci. Technol. 34(2): 339-371 (2019) - [c12]Dawen Xu, KouZi Xing, Cheng Liu, Ying Wang, Yulin Dai, Long Cheng, Huawei Li, Lei Zhang:
Resilient Neural Network Training for Accelerators with Computing Errors. ASAP 2019: 99-102 - [c11]Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li:
Exploring emerging CNFET for efficient last level cache design. ASP-DAC 2019: 426-431 - [c10]Shengwen Liang, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. FPL 2019: 173-179 - [c9]Cheng Liu, Xinyu Chen, Bingsheng He, Xiaofei Liao, Ying Wang, Lei Zhang:
OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs. FPT 2019: 315-318 - [c8]Li Li, Dawen Xu, Kouzi Xing, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li:
Squeezing the Last MHz for CNN Acceleration on FPGAs. ITC-Asia 2019: 151-156 - [r1]Xuntao Cheng, Cheng Liu, Bingsheng He:
Emerging Hardware Technologies. Encyclopedia of Big Data Technologies 2019 - [i4]Chuangyi Gui, Long Zheng, Bingsheng He, Cheng Liu, Xinyu Chen, Xiaofei Liao, Hai Jin:
A Survey on Graph Processing Accelerators: Challenges and Opportunities. CoRR abs/1902.10130 (2019) - 2018
- [c7]Dawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li:
FCN-engine: accelerating deconvolutional layers in classic CNN processors. ICCAD 2018: 22 - 2017
- [j4]Dongxing Bao, Xiaoming Li, Yizong Xin, Jiuru Yang, Xiangshi Ren, Fangfa Fu, Cheng Liu:
A Virtual Channel Allocation Algorithm for NoC. EAI Endorsed Trans. Ambient Syst. 4(14): e4 (2017) - [c6]Dongxing Bao, Xiaoming Li, Yizong Xin, Jiuru Yang, Xiangshi Ren, Fangfa Fu, Cheng Liu:
A Virtual Channel Allocation Algorithm for NoC. MLICOM (2) 2017: 333-342 - 2016
- [j3]Amelie Chi Zhou, Bingsheng He, Cheng Liu:
Monetary Cost Optimizations for Hosting Workflow-as-a-Service in IaaS Clouds. IEEE Trans. Cloud Comput. 4(1): 34-48 (2016) - [p1]Hayden Kwok-Hay So, Cheng Liu:
FPGA Overlays. FPGAs for Software Programmers 2016: 285-305 - [i3]Ho-Cheung Ng, Cheng Liu, Hayden Kwok-Hay So:
A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. CoRR abs/1606.06483 (2016) - 2015
- [j2]Ying Wang, Yinhe Han, Lei Zhang, Binzhang Fu, Cheng Liu, Huawei Li, Xiaowei Li:
Economizing TSV Resources in 3-D Network-on-Chip Design. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 493-506 (2015) - [c5]Cheng Liu, Hayden Kwok-Hay So:
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. FCCM 2015: 101 - [c4]Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So:
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. FPT 2015: 56-63 - [i2]Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So:
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. CoRR abs/1509.00042 (2015) - 2013
- [j1]Yinhe Han, Cheng Liu, Hang Lu, Wen-Bo Li, Lei Zhang, Xiaowei Li:
RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. J. Comput. Sci. Technol. 28(6): 1045-1053 (2013) - [c3]Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So:
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM 2013: 228 - [i1]Amelie Chi Zhou, Bingsheng He, Cheng Liu:
Probabilistic Scheduling of Scientific Workflows in Dynamic Cloud Environments. CoRR abs/1306.6410 (2013) - 2011
- [c2]Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. ASP-DAC 2011: 357-362 - [c1]Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li:
A resilient on-chip router design through data path salvaging. ASP-DAC 2011: 437-442
Coauthor Index
[j28] [j27] [j25] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [c38] [c37] [i19] [i18] [i17] [i16] [i14] [i13] [i12] [j12] [j11] [c35] [c34] [c33] [c32] [c31] [i11] [i9] [j10] [j9] [j8] [j7] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [i8] [i7] [i6] [i5] [j6] [c20] [c19] [c18] [c17] [c16] [c15] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [j2]
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