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ORCIDPrashant J. Nair
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2020 – today
- 2020
[c18]Beomjun Kim, Prashant J. Nair, Seokin Hong:
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches. ICCD 2020: 421-424
2010 – 2019
- 2019
- [c17]Prashant J. Nair, Bahar Asgari, Moinuddin K. Qureshi:
SuDoku: Tolerating High-Rate of Transient Failures for Enabling Scalable STTRAM. DSN 2019: 388-400 - [c16]Poulami Das, Swamit S. Tannu, Prashant J. Nair, Moinuddin K. Qureshi:
A Case for Multi-Programming Quantum Computers. MICRO 2019: 291-303 - [c15]Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. MICRO 2019: 453-465 - [i3]Seokin Hong, Bülent Abali, Alper Buyuktosunoglu, Michael B. Healy, Prashant J. Nair:
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads. CoRR abs/1909.00553 (2019) - 2018
- [c14]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi:
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories. HPCA 2018: 454-465 - [c13]Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-hyoun Kim, Michael B. Healy:
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. MICRO 2018: 326-338 - [c12]Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, José A. Joao, Moinuddin K. Qureshi:
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories. MICRO 2018: 416-427 - [i2]Kevin K. Chang, Prashant J. Nair, Saugata Ghose, Donghyuk Lee, Moinuddin K. Qureshi, Onur Mutlu:
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency. CoRR abs/1805.03184 (2018) - 2017
- [c11]Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi:
DICE: Compressing DRAM Caches for Bandwidth and Capacity. ISCA 2017: 627-638 - [c10]Swamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, Moinuddin K. Qureshi:
Taming the instruction bandwidth of quantum computers via hardware-managed error correction. MICRO 2017: 679-691 - [i1]Prashant J. Nair:
Architectural Techniques to Enable Reliable and Scalable Memory Systems. CoRR abs/1704.03991 (2017) - 2016
- [j4]Prashant J. Nair
, David A. Roberts, Moinuddin K. Qureshi:
FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems. ACM Trans. Archit. Code Optim. 12(4): 44:1-44:24 (2016) - [j3]Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi:
Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures. ACM Trans. Archit. Code Optim. 12(4): 49:1-49:24 (2016) - [c9]Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu:
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM. HPCA 2016: 568-580 - [c8]Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi:
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability. ISCA 2016: 341-353 - 2015
- [j2]Dae-Hyun Kim, Prashant J. Nair, Moinuddin K. Qureshi:
Architectural Support for Mitigating Row Hammering in DRAM Memories. IEEE Comput. Archit. Lett. 14(1): 9-12 (2015) - [c7]Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi:
DEUCE: Write-Efficient Encryption for Non-Volatile Memories. ASPLOS 2015: 33-44 - [c6]Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi:
Reducing Refresh Power in Mobile Devices with Morphable ECC. DSN 2015: 355-366 - [c5]Moinuddin K. Qureshi, Dae-Hyun Kim, Samira Manabi Khan, Prashant J. Nair, Onur Mutlu:
AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. DSN 2015: 427-437 - [c4]Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi:
Reducing read latency of phase change memory via early read and Turbo Read. HPCA 2015: 309-319 - 2014
- [j1]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
Refresh pausing in DRAM memory systems. ACM Trans. Archit. Code Optim. 11(1): 10:1-10:26 (2014) - [c3]Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi:
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures. MICRO 2014: 51-62 - 2013
- [c2]Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi:
A case for Refresh Pausing in DRAM memory systems. HPCA 2013: 627-638 - [c1]Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi:
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. ISCA 2013: 72-83
Coauthor Index
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