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ORCIDWeizheng Wang 0002
Person information
- affiliation: Changsha University of Science and Technology, Changsha, China
Other persons with the same name
- Weizheng Wang — disambiguation page
- Weizheng Wang 0001
![[0000-0002-5879-585X]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-5879-585X")
— City University of Hong Kong, Hong Kong - Weizheng Wang 0003 — Shandong Normal University, Jinan, China
- Weizheng Wang 0004 — Purdue University, West Lafayette, IN, USA
- Weizheng Wang 0005 — Delft University of Technology, Delft, The Netherlands
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2020 – today
- 2025
[j25]Weizheng Wang, Zhizhi Wu, Jinhai Chen, Peng Liu, Shuo Cai, Neal N. Xiong:
SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF. IEEE Internet Things J. 12(14): 28401-28414 (2025)- [j24]Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu:
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications. IEEE Trans. Very Large Scale Integr. Syst. 33(2): 475-487 (2025) - 2024
- [j23]Weizheng Wang, Xingxing Gong, Shuo Cai, Jiamin Liu, Xiangqi Wang:
A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation. IEEE Access 12: 182561-182570 (2024) - [j22]Weizheng Wang, Xingxing Gong, Xiangqi Wang, Shuo Cai, Peng Liu, Neal N. Xiong:
DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks. IEEE Internet Things J. 11(23): 38829-38845 (2024) - [j21]Weizheng Wang, Jinhai Chen, Xianmin Pan:
A secure scan architecture using dynamic key to thwart scan-based side-channel attacks. Microelectron. J. 143: 106050 (2024) - 2023
- [j20]Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin:
Four-input-C-element-based multiple-node-upset-self-recoverable latch designs. Integr. 90: 11-21 (2023) - [j19]Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu:
Low-power and high-speed SRAM cells for double-node-upset recovery. Integr. 91: 1-9 (2023) - [j18]Weizheng Wang, Jian Liang, Xiangqi Wang, Xianmin Pan, Shuo Cai:
A secure scan architecture using parallel latch-based lock. Integr. 93: 102067 (2023) - [j17]Shuo Cai, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li:
A highly reliable and low-power cross-coupled 18T SRAM cell. Microelectron. J. 134: 105729 (2023) - [c3]Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu:
A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design. ATS 2023: 1-5 - 2022
- [j16]Shuo Cai, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu:
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation. J. Electron. Test. 38(2): 165-180 (2022) - [j15]Weizheng Wang, Xiangqi Wang, Jin Wang, Neal N. Xiong, Shuo Cai, Peng Liu:
Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture. IEEE Trans. Syst. Man Cybern. Syst. 52(3): 2009-2023 (2022) - 2021
- [j14]Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han:
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. IEEE Trans. Emerg. Top. Comput. 9(2): 745-758 (2021) - [c2]Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang:
A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design. ITC-Asia 2021: 1-5 - 2020
- [j13]Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li:
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. J. Electron. Test. 36(4): 469-483 (2020)
2010 – 2019
- 2019
- [j12]Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai:
A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks. IEEE Access 7: 22206-22213 (2019) - [j11]Shuo Cai, Weizheng Wang, Fei Yu, Binyong He:
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. J. Electron. Test. 35(2): 163-172 (2019) - [j10]Lingyun Xiang, Xiao Yang, Jiahe Zhang, Weizheng Wang:
A word-frequency-preserving steganographic method based on synonym substitution. Int. J. Comput. Sci. Eng. 19(1): 132-139 (2019) - [j9]Weizheng Wang, Zhuo Deng, Jin Wang:
Enhancing Sensor Network Security with Improved Internal Hardware Design. Sensors 19(8): 1752 (2019) - [j8]Weizheng Wang, Zhuo Deng, Jin Wang, Arun Kumar Sangaiah, Shuo Cai, Zafer Al-Makhadmeh, Amr Tolba:
Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications. Sensors 19(20): 4598 (2019) - 2018
- [c1]Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai:
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. ATS 2018: 25-29 - 2017
- [j7]Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang:
Reliability evaluation of logic circuits based on transient faults propagation metrics. IEICE Electron. Express 14(7): 20170128 (2017) - 2016
- [j6]Fei Yu, Qiang Tang, Weizheng Wang, Honglin Wu:
A 2.7 GHz Low-Phase-Noise LC-QVCO Using the Gate-Modulated Coupling Technique. Wirel. Pers. Commun. 86(2): 671-681 (2016) - 2015
- [j5]Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Weizheng Wang:
Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. IEICE Electron. Express 12(23): 20150839 (2015) - 2013
- [j4]Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang:
Low power logic BIST with high test effectiveness. IEICE Electron. Express 10(23): 20130853 (2013) - 2012
- [j3]Zhiqiang You, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin:
A scan disabling-based BAST scheme for test cost and test power reduction. IEICE Electron. Express 9(2): 111-116 (2012) - [j2]Weizheng Wang, Jishun Kuang, Peng Liu, Xin Peng, Zhiqiang You:
Switching activity reduction for scan-based BIST using weighted scan input data. IEICE Electron. Express 9(10): 874-880 (2012) - 2011
- [j1]Zhiqiang You, Weizheng Wang, Zhiping Dou, Peng Liu, Jishun Kuang:
A scan disabling-based BAST scheme for test cost reduction. IEICE Electron. Express 8(16): 1367-1373 (2011)
Coauthor Index
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