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ORCIDYasuhisa Shimazaki
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2020 – today
- 2023
[c14]Kenichi Shimada, Keiichiro Sano, Kazuki Fukuoka, Hiroshi Morita, Masayuki Daito, Tatsuya Kamei, Hiroyuki Hamasaki, Yasuhisa Shimazaki:
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power. ISSCC 2023: 240-241- 2020
- [j9]Hiroyuki Kondo, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura
, Toshihiro Hattori, Noriaki Sakamoto, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Kosuke Yayama:
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. IEEE J. Solid State Circuits 55(1): 133-144 (2020)
2010 – 2019
- 2019
- [c13]Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo:
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. ISSCC 2019: 54-56 - 2017
- [j8]Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima:
A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard. IEEE J. Solid State Circuits 52(1): 77-88 (2017) - [c12]Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo:
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. ISSCC 2017: 58-59 - [c11]Yasuhisa Shimazaki, John Maneatis, Edith Beigné:
Session 8 overview: Digital PLLs and security circuits. ISSCC 2017: 140-141 - 2016
- [c10]Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji, Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita:
4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability. ISSCC 2016: 80-81 - 2013
- [j7]Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki:
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. IEEE J. Solid State Circuits 48(4): 917-923 (2013) - 2012
- [c9]Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda:
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips 2012: 1-3 - [c8]Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki:
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238 - [c7]Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki:
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. VLSIC 2012: 58-59 - 2010
- [j6]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010)
2000 – 2009
- 2009
- [c6]Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704 - [c5]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2008
- [c4]Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC 2008: 384-385 - 2007
- [j5]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. IEEE J. Solid State Circuits 42(1): 74-83 (2007) - 2006
- [j4]Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara:
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41(3): 705-711 (2006) - [c3]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c2]Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. ISSCC 2006: 2200-2209 - [c1]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. ISSCC 2006: 2210-2219 - 2005
- [j3]Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori:
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Trans. Electron. 88-C(4): 528-535 (2005) - [j2]Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada:
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits 40(1): 186-194 (2005) - 2004
- [j1]Yasuhisa Shimazaki, Radu Zlatanovici, Borivoje Nikolic:
A shared-well dual-supply-voltage 64-bit ALU. IEEE J. Solid State Circuits 39(3): 494-500 (2004)
Coauthor Index
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