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Publication search results
found 190 matches
- 2019
- Ying Wang, Huawei Li, Long Cheng, Xiaowei Li:
A QoS-QoR Aware CNN Accelerator Design Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 1995-2007 (2019) - Yi Wang, Mingxu Zhang, Xuan Yang, Tao Li:
A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 617-627 (2019) - Iskren Abdomerovic, Sanjay Raman:
A Millimeter Wave Loss-Aware Methodology for Switchless PALNA Integrated Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2177-2190 (2019) - Armin Haj Aboutalebi, Ethan C. Ahn, Bo Mao, Suzhen Wu, Lide Duan:
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2229-2242 (2019) - Antara Ain, Pallab Dasgupta:
Interpreting Local Variables in AMS Assertions During Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 980-984 (2019) - Bijan Alizadeh, Seyyed Reza Sharafinejad:
Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 245-252 (2019) - Matthew Layne Beckler, Ronald D. Blanton:
On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 322-334 (2019) - Sukanta Bhattacharjee, Ansuman Banerjee, Tsung-Yi Ho, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 874-887 (2019) - Philip Brisk, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatié, Swaroop Ghosh, Xun Jiao:
TCAD EIC Message: February 2019. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 197-198 (2019) - Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto:
Logic Synthesis for Interpolant Circuit Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 380-384 (2019) - Keith A. Campbell, Chen-Hsuan Lin, Deming Chen:
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1056-1069 (2019) - Keith A. Campbell, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen:
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1345-1358 (2019) - Xuebing Cao, Liyi Xiao, Jie Li, Rongsheng Zhang, Shanshan Liu, Jinxiang Wang:
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1109-1122 (2019) - Kun Cao, Guo Xu, Junlong Zhou, Tongquan Wei, Mingsong Chen, Shiyan Hu:
QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware IoT Lifetime Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1799-1810 (2019) - Kun Cao, Junlong Zhou, Peijin Cong, Liying Li, Tongquan Wei, Mingsong Chen, Shiyan Hu, Xiaobo Sharon Hu:
Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1189-1202 (2019) - Christine S. Chan, Alper Sinan Akyürek, Baris Aksanli, Tajana Simunic Rosing:
Optimal Performance-Aware Cooling on Enterprise Servers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1689-1702 (2019) - Da-Wei Chang, Ing-Chao Lin, Yi-Chiao Lin, Wen-Zhi Huang:
OCMAS: Online Page Clustering for Multibank Scratchpad Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 220-233 (2019) - Wei-Ming Chen, Sheng-Wei Cheng, Pi-Cheng Hsiu:
A User-Centric CPU-GPU Governing Framework for 3-D Mobile Games. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 961-974 (2019) - Song Chen, Qi Xu, Bei Yu:
Adaptive 3D-IC TSV Fault Tolerance Structure Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 949-960 (2019) - Yen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Chen, Hsin-Wen Wei, Wei-Kuan Shih:
Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 29-42 (2019) - Renhai Chen, Chi Zhang, Yi Wang, Zhaoyan Shen, Duo Liu, Zili Shao, Yong Guan:
DCR: Deterministic Crash Recovery for NAND Flash Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2201-2214 (2019) - Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang:
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1717-1730 (2019) - Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li:
Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 767-779 (2019) - Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel:
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1305-1316 (2019) - Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang:
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 834-847 (2019) - Jaeyong Cho, Karam Hwang, Seungil Jeung, Seungyoung Ahn:
An Efficient Extrapolation Method of Band-Limited S-Parameters for Extracting Causal Impulse Responses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2086-2098 (2019) - Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 551-561 (2019) - Suhyeong Choi, Seongbo Shim, Youngsoo Shin:
Neural Network Classifier-Based OPC With Imbalanced Training Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 938-948 (2019) - Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri:
Translation Validation of Code Motion Transformations Involving Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1378-1382 (2019) - Jaeyong Chung, Taehwan Shin, Joon-Sung Yang:
Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2032-2042 (2019)
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