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2020 – today
- 2021
[c57]Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin:
Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. VTS 2021: 1-6- 2020
- [j17]Liyang Lai
, Kun-Han Tsai, Huawei Li:
GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 239-247 (2020) - [j16]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng:
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3044-3055 (2020) - [c56]Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin:
Test Challenges of Intel IA Cores. ITC 2020: 1-5 - [c55]Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng:
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. ITC-Asia 2020: 118-123
2010 – 2019
- 2019
- [c54]Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng:
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. ASP-DAC 2019: 341-346 - [c53]Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz:
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS 2019: 19-24 - [c52]Kun-Han Tsai:
Race and Glitch Handling: A Test Perspective. ITC-Asia 2019: 85-90 - 2018
- [j15]Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Circuit and Methodology for Testing Small Delay Faults in the Clock Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2087-2097 (2018) - [c51]Kun-Han Tsai:
X-Sources Analysis for Improving the Test Quality. ITC-Asia 2018: 121-126 - 2017
- [c50]Kun-Han Tsai, Srinivasan Gopalakrishnan:
Test Coverage Analysis for Designs with Timing Exceptions. ATS 2017: 169-174 - 2016
- [j14]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng:
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33(2): 9-16 (2016) - [j13]Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng:
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33(6): 23-30 (2016) - [c49]Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Testing of small delay faults in a clock network. ETS 2016: 1-6 - [c48]Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng:
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS 2016: 125-129 - [c47]Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng:
Online slack-time binning for IO-registered die-to-die interconnects. ITC 2016: 1-8 - 2015
- [j12]Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1836-1846 (2015) - [j11]Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2039-2048 (2015) - [c46]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng:
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE 2015: 924-927 - [c45]Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Monitoring the delay of long interconnects via distributed TDC. ITC 2015: 1-9 - [c44]Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng:
A test-application-count based learning technique for test time reduction. VLSI-DAT 2015: 1-4 - [c43]Kun-Han Tsai, Janusz Rajski:
Clock-domain-aware test for improving pattern compression. VLSI-DAT 2015: 1-4 - 2014
- [j10]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 476-488 (2014) - [j9]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1258-1268 (2014) - [c42]Kun-Han Tsai:
Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs. ATS 2014: 119-124 - [c41]Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs. ATS 2014: 162-167 - [c40]Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng:
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. ETS 2014: 1-2 - 2013
- [j8]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 737-747 (2013) - [j7]Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1265-1273 (2013) - [j6]Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng:
Oscillation-Based Prebond TSV Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1440-1444 (2013) - [c39]Kun-Han Tsai, Xijiang Lin:
Multicycle-aware At-speed Test Methodology. Asian Test Symposium 2013: 49 - [c38]Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
Mid-bond Interposer Wire Test. Asian Test Symposium 2013: 153-158 - [c37]Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng:
At-speed BIST for interposer wires supporting on-the-spot diagnosis. IOLTS 2013: 67-72 - [c36]Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng:
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs. ITC 2013: 1-8 - [c35]Kun-Han Tsai, Shuo Sheng:
Design rule check on the clock gating logic for testability and beyond. ITC 2013: 1-8 - [c34]Jiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng:
Improve speed path identification with suspect path expressions. VLSI-DAT 2013: 1-4 - 2012
- [c33]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Programmable Leakage Test and Binning for TSVs. Asian Test Symposium 2012: 43-48 - [c32]Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai:
Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036 - [c31]Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10 - 2010
- [c30]Meng-Fan Wu, Hsin-Cheih Pan, Teng-Han Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng:
Improved weight assignment for logic switching activity during at-speed test pattern generation. ASP-DAC 2010: 493-498 - [c29]Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz:
Scan based speed-path debug for a microprocessor. ETS 2010: 207-212 - [c28]Chih-Peng Li, Sen-Hung Wang, Kun-Han Tsai:
A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems. ICC 2010: 1-5 - [c27]Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli:
A scalable quantitative measure of IR-drop effects for scan pattern generation. ICCAD 2010: 162-167 - [c26]Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli:
Test cycle power optimization for scan-based designs. ITC 2010: 134-143
2000 – 2009
- 2009
- [j5]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 245-258 (2009) - [c25]Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng:
At-Speed Scan Test Method for the Timing Optimization and Calibration. Asian Test Symposium 2009: 430-433 - [c24]Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai:
Speed-Path Debug Using At-Speed Scan Test Patterns. ETS 2009: 11-16 - 2008
- [j4]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 932-945 (2008) - [c23]Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake:
Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS 2008: 179-184 - [c22]Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng:
A Robust Automated Scan Pattern Mismatch Debugger. ATS 2008: 309-314 - [c21]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253 - 2007
- [c20]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski:
Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693 - [c19]Teresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim:
Enhanced testing of clock faults. ITC 2007: 1-9 - 2006
- [j3]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 558-575 (2006) - [c18]Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo:
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS 2006: 139-146 - [c17]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo:
At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS 2006: 153-162 - [c16]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472 - [c15]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10 - [c14]Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich:
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC 2006: 1-9 - [c13]Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami:
Improved Handling of False and Multicycle Paths in ATPG. VTS 2006: 160-165 - 2005
- [j2]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1315-1325 (2005) - [c12]Grady Giles, Joel Irby, Daniela Toneva, Kun-Han Tsai:
Built-in constraint resolution. ITC 2005: 10 - [c11]Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai:
Compression mode diagnosis enables high volume monitoring diagnosis flow. ITC 2005: 10 - 2004
- [c10]Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski:
Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209 - [c9]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Diagnosis of Hold Time Defects. ICCD 2004: 192-199 - [c8]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490 - [c7]Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533 - 2003
- [c6]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198- - [c5]Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338 - [c4]Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski:
Impact of Multiple-Detect Test Patterns on Product Quality. ITC 2003: 1031-1040 - 2002
- [c3]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310 - 2000
- [j1]Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska:
Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1052-1064 (2000)
1990 – 1999
- 1997
- [c2]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477 - [c1]Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski:
Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556
Coauthor Index
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