IEEE Transactions on Computers, Volume 48

Volume 48, Number 1, January 1999

Computer Arithmetic

• 
  Alberto Nannarelli, Tomás Lang:
  Low-Power Divider. 2-14
• 
  Kiamal Z. Pekmastzi:
  Multiplexer-Based Array Multipliers. 15-23

Software Testing

• 
  Aki W. Tomita, Ken Sakamura:
  Improving Design Dependability by Exploiting an Open Model-Based Specification. 24-37

Fault Tolerance

• 
  Andreas Savva, Takashi Nanya:
  A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. 38-52

Real-Time Systems

• 
  Christopher A. Healy, Robert D. Arnold, Frank Mueller, David B. Whalley, Marion G. Harmon:
  Bounding Pipeline and Instruction Cache Performance. 53-70

Brief Contributions

• 
  Hoang Pham, Xuemei Zhang:
  A Software Cost Model with Warranty and Risk Costs. 71-75
• 
  Naofumi Takagi, Takashi Horiyama:
  A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival. 76-80
• 
  Yuh-Rong Leu, Sy-Yen Kuo:
  Distributed Fault-Tolerant Ring Embedding and Reconfiguration in Hypercubes. 81-88
• 
  Feng Cao, Ding-Zhu Du, D. Frank Hsu, Shang-Hua Teng:
  Fault Tolerance Properties of Pyramid Networks. 88-93

Volume 48, Number 2, February 1999

Special Issue on Cache Memory and Related Problems

• 
  Veljko M. Milutinovic, Mateo Valero:
  Enhancing and Exploiting the Locality. 97-99

Uniprocessing

• 
  Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith:
  Functional Implementation Techniques for CPU Cache Memories. 100-110
• 
  Eric Rotenberg, Steve Bennett, James E. Smith:
  A Trace Cache Microarchitecture and Evaluation. 111-120
• 
  Doug Joseph, Dirk Grunwald:
  Prefetching Using Markov Predictors. 121-133
• 
  Chi-Keung Luk, Todd C. Mowry:
  Automatic Compiler-Inserted Prefetching for Pointer-Based Applications. 134-141
• 
  Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau:
  Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. 142-149
• 
  Olivier Temam:
  An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels. 150-158
• 
  Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary:
  Improving Cache Locality by a Combination of Loop and Data Transformation. 159-167
• 
  John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis:
  Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance. 168-175
• 
  Hantak Kwak, Ben Lee, Ali R. Hurson, Suk-Han Yoon, Woo-Jong Hahn:
  Effects of Multithreading on Cache Performance. 176-184
• 
  Nigel P. Topham, Antonio González:
  Randomized Cache Placement for Eliminating Conflicts. 185-192
• 
  Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt:
  Evaluation of Design Options for the Trace Cache Fetch Mechanism. 193-204

Multiprocessing

• 
  Mark A. Heinrich, Vijayaraghavan Soundararajan, John L. Hennessy, Anoop Gupta:
  A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory. 205-217
• 
  Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve:
  The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. 218-226
• 
  Seungjoon Park, David L. Dill:
  An Executable Specification and Verifier for Relaxed Memory Order. 227-235
• 
  Donglai Dai, Dhabaleswar K. Panda:
  Exploiting the Benefits of Multiple-Path Network DSM Systems: Architectural Alternatives and Performance Evaluation. 236-244
• 
  Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim:
  Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. 245-255
• 
  Zheng Zhang, Marcelo H. Cintra, Josep Torrellas:
  Excel-NUMA: Toward Programmability, Simplicity, and High Performance. 256-264

Volume 48, Number 3, March 1999

Interconnection Networks

• 
  Yuanyuan Yang, Jianchao Wang:
  Wide-Sense Nonblocking Clos Networks Under Packing Strategy. 265-284

Cellular Automata

• 
  Kevin Cattell, Shujian Zhang, Micaela Serra, Jon C. Muzio:
  2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application. 285-295

Logic Design

• 
  Fabrizio Luccio, Linda Pagli:
  On a New Boolean Function with Applications. 296-310

Diagnosis and Testing

• 
  Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
  Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. 311-322

Brief Contributions

• 
  Elizabeth M. Rudnick, Janak H. Patel:
  Efficient Techniques for Dynamic Test Sequence Compaction. 323-330
• 
  Tong Sun, Qing Yang:
  A Comparative Analysis of Cache Designs for Vector Processing. 331-344
• 
  Anna Bernasconi, Bruno Codenotti:
  Spectral Analysis of Boolean Functions as a Graph Eigenvalue Problem. 345-351
• 
  Yeimkuan Chang, Laxmi N. Bhuyan:
  An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors. 352-360

Volume 48, Number 4, April 1999

Graph Partitioning

• 
  Roberto Battiti, Alan A. Bertossi:
  Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning. 361-385

Fault Tolerance

• 
  Chung-Ho Chen, Arun K. Somani:
  Fault Containment in Cache Memories for TMR Redundant Processor Systems. 386-397
• 
  Laurence E. LaForge:
  Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types. 398-416

Hardware/Software Design of Embedded Systems

• 
  Bharat P. Dave, Niraj K. Jha:
  COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. 417-441

Diagnosis and Testing

• 
  Michael J. Liebelt, Neil Burgess:
  Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits. 442-448

Brief Contributions

• 
  Anna M. del Corral, José M. Llabería:
  Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems. 449-456

Volume 48, Number 5, May 1999

Processor Architecture

• 
  Chien-Ming Chen, Chung-Ta King:
  Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction. 457-469

Fault Tolerance and Diagnosis

• 
  Douglas M. Blough, Hongying W. Brown:
  The Broadcast Comparison Model for On-Line Fault Diagnosis in Multicomputer Systems. 470-493

Memory Hierarchies for Shared-Memory Multiprocessors

• 
  Chun Xia, Josep Torrellas:
  Comprehensive Hardware and Software Support for Operating Systems to Exploit. 494-505

Satisfiability

• 
  João P. Marques Silva, Karem A. Sakallah:
  GRASP: A Search Algorithm for Propositional Satisfiability. 506-521

Brief Contributions

• 
  Berk Sunar, Çetin Kaya Koç:
  Mastrovito Multiplier for All Trinomials. 522-527
• 
  Karama Kanoun, Marie Borrel, Thierry Morteveille, Alain Peytavin:
  Availability of CAUTRA, a Subset of the French Air Traffic Control System. 528-535
• 
  Debasish Das, Mallika De, Bhabani P. Sinha:
  A New Network Topology with Multiple Meshes. 536-551

Volume 48, Number 6, June 1999

Special Section on Configurable Computing

• 
  Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni, Jean-Luc Beuchat, André Stauffer, Andrés Pérez-Uribe:
  Static and Dynamic Configurable Systems. 556-564
• 
  Douglas Chang, Malgorzata Marek-Sadowska:
  Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. 565-578
• 
  Karthikeya M. Gajjala Purna, Dinesh Bhatia:
  Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. 579-590
• 
  Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook:
  Dynamic Reconfiguration to Support Concurrent Applications. 591-602
• 
  Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
  Synthesis of Application Specific Instructions for Embedded DSP Software. 603-614
• 
  Claude Thibeault, Guy Bégin:
  A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations. 615-627
• 
  Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi:
  The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. 628-639

Brief Contributions

• 
  Paul D. Fiore:
  Parallel Multiplication Using Fast Sorting Networks. 640-645

Volume 48, Number 7, July 1999

Interconnection Networks

• 
  Timothy Mark Pinkston:
  Flexible and Efficient Routing Based on Progressive Deadlock Recovery. 649-669

Parallel Computation

• 
  Mark W. Goudreau, Kevin J. Lang, Satish Rao, Torsten Suel, Thanasis Tsantilas:
  Portable and Efficient Parallel Computing Using the BSP Model. 670-689

Algorithms for Systolic Arrays

• 
  Chih-Wei Liu, Kuo-Tai Huang, Chung-Chin Lu:
  A Systolic Array Implementation of the Feng-Rao Algorithm. 690-706

Fault Tolerance

• 
  Michel Cukier, David Powell, Jean Arlat:
  Coverage Estimation Methods for Stratified Fault Injection. 707-723

Brief Contributions

• 
  Janusz Rajski, Jerzy Tyszer:
  Diagnosis of Scan Cells in BIST Environment. 724-731
• 
  Jenn-Yang Ke, Jong-Chuang Tsay:
  An Approach to Checking Link Conflicts in the Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. 732-737
• 
  Si-Qing Zheng, M. Sun:
  Constructing Optimal Search Trees in Optimal Time. 738-743
• 
  Takashi Harada, Masafumi Yamashita:
  Improving the Availability of Mutual Exclusion Systems on Incomplete Networks. 744-747
• 
  Antonio García, Antonio Lloris-Ruíz:
  A Look-Up Scheme for Scaling in the RNS. 748-751
• 
  Savio S. H. Tse, Francis C. M. Lau:
  On the Space Requirement of Interval Routing. 752-757
• 
  Qian-Yu Tang, Xiaoyu Song:
  Diagnosis of Parallel Computers with Arbitrary Connectivity. 757-761
• 
  Pradeep Prabhakaran, Prithviraj Banerjee:
  Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. 762-768

Volume 48, Number 8, August 1999

Logic Synthesis

• 
  Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino:
  Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. 769-779

Systems Architecture

• 
  Chung-Ho Chen, Feng-Fu Lin:
  An Easy-to-Use Approach for Practical Bus-Based System Design. 780-793

Error Correcting Code

• 
  Luca G. Tallini, Bella Bose:
  Balanced Codes with Parallel Encoding and Decoding. 794-814

Fault Tolerance

• 
  Wen-Feng Chang, Cheng-Wen Wu:
  Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. 815-826

Computer Arithmetik

• 
  Tomás Lang, Paolo Montuschi:
  Very High Radix Square Root with Prescaling and Rounding and a Combined Division/Square Root Unit. 827-841

Brief Contributions

• 
  Michael J. Schulte, James E. Stine:
  Approximating Elementary Functions with Symmetric Bipartite Tables. 842-847
• 
  Huapeng Wu, M. Anwarul Hasan:
  Closed-Form Expression for the Average Weight of Signed-Digit Representations. 848-851
• 
  Richard Conway, John S. Nelson:
  Fast Converter for 3 Moduli RNS Using New Property of CRT. 852-860
• 
  Bogdan J. Falkowski:
  A Note on the Polynomial Form of Boolean Functions and Related Topics. 860-864

Volume 48, Number 9, September 1999

Special Section on Multithreaded Architecture

• 
  Venkata Krishnan, Josep Torrellas:
  A Chip-Multiprocessor Architecture with Speculative Multithreading. 866-880
• 
  Jenn-Yuan Tsai, Jian Huang, Christoffer Amlo, David J. Lilja, Pen-Chung Yew:
  The Superthreaded Processor Architecture. 881-902
• 
  Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally:
  Concurrent Event Handling through Multithreading. 903-916

ATM Networks

• 
  Amitava Raha, Sanjay Kamat, Xiaohua Jia, Wei Zhao:
  Using Traffic Regulation to Meet End-to-End Deadlines in ATM Networks. 917-935

Testing

• 
  Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
  An Effective Built-In Self-Test Scheme for Parallel Multipliers. 936-950

Parallel Processing

• 
  Francescomaria Marino, Earl E. Swartzlander Jr.:
  Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. 951-961

Logic Synthesis

• 
  Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska:
  Circuit Optimization by Rewiring. 962-970

Verification

• 
  John D. Lafferty, Alexander Vardy:
  Ordered Binary Decision Diagrams and Minimal Trellises. 971-987

Brief Contributions

• 
  Rolf Drechsler:
  Preudo-Kronecker Expressions for Symmetric Functions. 987-990
• 
  Susanto Rahardja, Bogdan J. Falkowski:
  Fast Linearly Independent Arithmetic Expansions. 991-999
• 
  Peichen Pan, C. L. Liu:
  Partial Scan with Preselected Scan Signals. 1000-1005

Volume 48, Number 10, October 1999

Cache Memory Systems

• 
  John Stuart Harper, Darren J. Kerbyson, Graham R. Nudd:
  Analytical Modeling of Set-Associative Cache Behavior. 1009-1024

Cryptography

• 
  Christof Paar, Peter Fleischmann, Pedro Soria-Rodriguez:
  Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents. 1025-1034

Real-Time Systems

• 
  Giorgio C. Buttazzo, Fabrizio Sensini:
  Optimal Deadline Assignment for Scheduling Soft Aperiodic Tasks in Hard Real-Time Environments. 1035-1052

Fault Tolerance

• 
  Gregory H. Chisholm, Anthony S. Wojcik:
  An Application of Formal Analysis to Software in a Fault-Tolerant Environment. 1053-1064

Networks

• 
  Yu-Chee Tseng, Sze-Yao Ni, Jang-Ping Sheu:
  Toward Optimal Complete Exchange on Wormhole-Routed Tori. 1065-1082

Computer Arithmetic

• 
  Javier D. Bruguera, Tomás Lang:
  Leading-One Prediction with Concurrent Position Correction. 1083-1097
• 
  Vassil S. Dimitrov, Graham A. Jullien, William C. Miller:
  Theory and Applications of the Double-Base Number System. 1098-1106

FPGA Architecture

• 
  Guang-Ming Wu, Yao-Wen Chang:
  Quasi-Universal Switch Matrices for FPD Design. 1107-1122

Brief Contributions

• 
  Satoshi Fujita:
  A Fault-Tolerant Broadcast Scheme in the Star Graph under the Single-Port, Half-Duplex Communication Model. 1123-1126
• 
  P. P. Chakrabarti:
  Partial Precedence Constrained Scheduling. 1127-1130
• 
  Geetha Panchapakesan, Abhijit Sengupta:
  On a Lightwave Network Topology Using Kauts Digraphs. 1131-1138
• 
  Dimitris Nikolos, Haridimos T. Vergos:
  On the Yield of VLSI Processors with On-Chip CPU Cache. 1138-1144
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. 1145-1152

Volume 48, Number 11, November 1999

Testing

• 
  Asger Munk Nielsen, Peter Kornerup:
  Redundant Radix Representations of Rings. 1153-1165
• 
  Bruno Sericola:
  Availability Analysis of Repairable Computer Systems and Stationarity Detection. 1166-1172

System Performance

• 
  Kenneth E. Hoganson:
  Workload Execution Strategies and Parallel Speedup on Clustered Computers. 1173-1182

Dependability of Computing Systems

• 
  Timothy K. Tsai, Mei-Chen Hsueh, Hong Zhao, Zbigniew Kalbarczyk, Ravishankar K. Iyer:
  Stress-Based and Path-Based Fault Injection. 1183-1201

Scheduling in Multiprocessors

• 
  Sivarama P. Dandamudi, Samir Ayachi:
  Performance of Hierarchical Processor Scheduling in Shared-Memory Multiprocessor Systems. 1202-1213

Interconnection Network Routing

• 
  Yuanyuan Yang, Gerald M. Masson:
  The Necessary Conditions for Clos-Type Nonblocking Multicast Networks. 1214-1227

Networks

• 
  Chao-Ju Hou:
  Routing Virtual Circuits with Temporal QoS Requirements in Virtual Path-Based ATM Networks. 1228-1243

Cache Memory Systems

• 
  Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson:
  Active Management of Data Caches by Exploiting Reuse Information. 1244-1259

Processor Architecture

• 
  Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark:
  Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. 1260-1281

Fault Tolerance

• 
  Yu-Chee Tseng, Ming-Hour Yang, Tong-Ying Juang:
  Achieving Fault-Tolerant Multicast in Injured Wormhole-Routed Tori and Meshes Based on Euler Path Construction. 1282-1296

Volume 48, Number 12, 1999

Routing

• 
  Mohamed Ould-Khaoua:
  A Performance Model for Duato's Fully Adaptive Routing Algorithm in k-Ary n-Cubes. 1297-1304

Testability

• 
  Franco Fummi, Donatella Sciuto, Micaela Serra:
  Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal. 1305-1323

Computer Arithmetic

• 
  José Fernández Ramos, Alfonso Gago Bohórquez:
  Two Operand Binary Adders with Threshold Logic. 1324-1337

Architecture

• 
  Teresa L. Johnson, Daniel A. Connors, Matthew C. Merten, Wen-mei W. Hwu:
  Run-Time Cache Bypassing. 1338-1354

Brief Contributions

• 
  Xin Yuan, Rami G. Melhem, Rajiv Gupta:
  Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks. 1355-1363
• 
  Jacob Savir:
  Distributed Generation of Weighted Random Patterns. 1364-1368
• 
  Dajin Wang:
  Diagnosability of Hypercubes and Enhanced Hypercubes under the Comparison Diagnosis Model. 1369-1374
• 
  Michael A. Iverson, Füsun Özgüner, Lee C. Potter:
  Statistical Prediction of Task Execution Times through Analytic Benchmarking for Scheduling in a Heterogeneous Environment. 1374-1379