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Sheqin Dong
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Publications
- 2014
- [i4]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR abs/1402.2460 (2014) - [i3]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Floorplanning and Topology Generation for Application-Specific Network-on-Chip. CoRR abs/1402.2462 (2014) - [i1]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR abs/1402.3149 (2014) - 2013
- [c69]Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto:
Delay-driven layer assignment in global routing under multi-tier interconnect structure. ISPD 2013: 101-107 - 2012
- [j23]Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto:
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. IEICE Trans. Electron. 95-C(4): 534-545 (2012) - [j22]Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto:
Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2208-2219 (2012) - [c68]Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto:
Linear optimal one-sided single-detour algorithm for untangling twisted bus. ASP-DAC 2012: 151-156 - 2011
- [c65]Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto:
Through-Silicon-Via assignment for 3D ICs. ASICON 2011: 353-356 - [c63]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC 2011: 473-478 - [c62]Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto:
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. ISQED 2011: 144-149 - [c61]Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto:
Novel and efficient min cut based voltage assignment in gate level. ISQED 2011: 150-155 - 2010
- [c60]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Floorplanning and topology generation for application-specific network-on-chip. ASP-DAC 2010: 535-540 - [c58]Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto:
A revisit to voltage partitioning problem. ACM Great Lakes Symposium on VLSI 2010: 115-118 - 2009
- [j16]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Voltage and Level-Shifter Assignment Driven Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2990-2997 (2009) - [c55]Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen:
Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI 2009: 51-56 - 2006
- [j11]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [c35]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
Buffer planning based on block exchanging. ISCAS 2006 - 2005
- [j10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c25]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299 - [c22]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c19]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c18]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c17]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j8]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j7]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [c16]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c15]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - 2003
- [j4]Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu:
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3136-3147 (2003) - [c13]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c12]Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu:
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC 2003: 741-744 - [c11]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c10]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c9]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142
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