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Books and Theses
- 1970
[b1]Sharad C. Seth:
Fault Testing in Combinational Cellular Arrays. University of Illinois Urbana-Champaign, USA, 1970
Journal Articles
- 2016
- [j31]David W. Embley, Mukkai S. Krishnamoorthy, George Nagy
, Sharad C. Seth:
Converting heterogeneous statistical tables on the web to searchable databases. Int. J. Document Anal. Recognit. 19(2): 119-138 (2016) - 2014
- [j30]Dongyuan Zhan, Hong Jiang, Sharad C. Seth:
CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches. IEEE Trans. Computers 63(7): 1656-1667 (2014) - 2010
- [j29]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. J. Low Power Electron. 6(3): 457-468 (2010) - 2009
- [j28]George Nagy, Sharad C. Seth, Mahesh Viswanathan:
Comment: Projection Methods Require Black Border Removal. IEEE Trans. Pattern Anal. Mach. Intell. 31(4): 762 (2009) - 2008
- [j27]Indranil Saha, Bhargab B. Bhattacharya, Sheng Zhang, Sharad C. Seth:
Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. Fundam. Informaticae 89(2-3): 331-344 (2008) - 2004
- [j26]Ashok Samal, Sharad C. Seth, Kevin Cueto:
A feature-based approach to conflation of geospatial sources. Int. J. Geogr. Inf. Sci. 18(5): 459-489 (2004) - 2003
- [j25]Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
Modeling Fault Coverage of Random Test Patterns. J. Electron. Test. 19(3): 271-284 (2003) - 2000
- [j24]Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu:
Integrated text and line-art extraction from a topographic map. Int. J. Document Anal. Recognit. 2(4): 177-185 (2000) - 1999
- [j23]Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
A synthesis for testability scheme for finite state machines using clock control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1780-1792 (1999) - 1997
- [j22]Yuhong Yu, Ashok Samal, Sharad C. Seth:
A system for recognizing a large class of engineering drawings. IEEE Trans. Pattern Anal. Mach. Intell. 19(8): 868-890 (1997) - 1995
- [j21]Paul Kenyon, Sharad C. Seth, Andrea Clematis, Prathima Agrawal, Gabriella Dodero, Vittoria Gianuzzi:
Programming pipelined CAD applications on message-passing architectures. Concurr. Pract. Exp. 7(4): 315-337 (1995) - [j20]N. Ranganathan, Sharad C. Seth:
Conference Reports. IEEE Des. Test Comput. 12(2): 5, 81 (1995) - [j19]Kent L. Einspahr, Sharad C. Seth:
A switch-level test generation system for synchronous and asynchronous circuits. J. Electron. Test. 6(1): 59-73 (1995) - 1994
- [j18]Yuhong Yu, Ashok Samal, Sharad C. Seth:
Isolating symbols from connection lines in a class of engineering drawings. Pattern Recognit. 27(3): 391-404 (1994) - 1993
- [j17]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
Generating Tests for Delay Faults in Nonscan Circuits. IEEE Des. Test Comput. 10(1): 20-28 (1993) - [j16]Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan:
Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. IEEE Trans. Pattern Anal. Mach. Intell. 15(7): 737-747 (1993) - [j15]D. Das, Sharad C. Seth, Vishwani D. Agrawal:
Accurate computation of field reject ratio based on fault latency. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 537-545 (1993) - 1992
- [j14]George Nagy, Sharad C. Seth, Mahesh Viswanathan:
A Prototype Document Image Analysis System for Technical Journals. Computer 25(7): 10-22 (1992) - 1990
- [j13]Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat:
A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990) - 1989
- [j12]Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. Integr. 7(1): 49-75 (1989) - [j11]Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. Integr. 7(3): 325 (1989) - [j10]Lester Lipsky, Sharad C. Seth:
Signal Probabilities in AND-OR Trees. IEEE Trans. Computers 38(11): 1558-1563 (1989) - [j9]Bhargab B. Bhattacharya, Sharad C. Seth:
Design of Parity Testable Combinational Circuits. IEEE Trans. Computers 38(11): 1580-1584 (1989) - 1987
- [j8]George Nagy, Sharad C. Seth, Kent L. Einspahr:
Decoding Substitution Ciphers by Means of Word Matching with Application to OCR. IEEE Trans. Pattern Anal. Mach. Intell. 9(5): 710-715 (1987) - 1984
- [j7]Ten-Chuan Hsiao, Sharad C. Seth:
An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. IEEE Trans. Computers 33(10): 934-937 (1984) - [j6]Sharad C. Seth, Vishwani D. Agrawal:
Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(2): 123-126 (1984) - 1983
- [j5]Sharad C. Seth, Lester Lipsky:
A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. IEEE Trans. Computers 32(8): 754-760 (1983) - 1981
- [j4]Sharad C. Seth, K. Narayanaswamy:
A Graph Model for Pattern-Sensitive Faults in Random Access Memories. IEEE Trans. Computers 30(12): 973-977 (1981) - 1978
- [j3]Kolar L. Kodandapani, Sharad C. Seth:
On Combinational Networks with Restricted Fan-Out. IEEE Trans. Computers 27(4): 309-318 (1978) - 1977
- [j2]James M. Steckelberg, Sharad C. Seth:
On a Relation Between Algebraic Programs and Turing Machines. Inf. Process. Lett. 6(6): 180-183 (1977) - [j1]Sharad C. Seth, Kolar L. Kodandapani:
Diagnosis of Faults in Linear Tree Networks. IEEE Trans. Computers 26(1): 29-33 (1977)
Conference and Workshop Papers
- 2018
- [c60]Zhichao Yan, Hong Jiang, Witawas Srisa-an, Sharad C. Seth, Yujuan Tan:
Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. ICPP 2018: 60:1-60:10 - 2017
- [c59]Junjie Qian, Hong Jiang, Witawas Srisa-an, Sharad C. Seth, Stan Skelton, Joseph Moore:
Energy-efficient I/O Thread Schedulers for NVMe SSDs on NUMA. CCGrid 2017: 569-578 - 2016
- [c58]George Nagy, Sharad C. Seth:
Table headers: An entrance to the data mine. ICPR 2016: 4065-4070 - [c57]Junjie Qian, Witawas Srisa-an, Sharad C. Seth, Hong Jiang, Du Li, Pan Yi:
Exploiting FIFO Scheduler to Improve Parallel Garbage Collection Performance. VEE 2016: 109-121 - 2015
- [c56]George Nagy, David W. Embley, Mukkai S. Krishnamoorthy, Sharad C. Seth:
Clustering header categories extracted from web tables. DRR 2015: 94020M - [c55]Junjie Qian, Du Li, Witawas Srisa-an, Hong Jiang, Sharad C. Seth:
Factors affecting scalability of multithreaded Java applications on manycore systems. ISPASS 2015: 167-168 - [c54]Junjie Qian, Witawas Srisa-an, Du Li, Hong Jiang, Sharad C. Seth, Yaodong Yang:
SmartStealing: Analysis and Optimization of Work Stealing in Parallel Garbage Collection for Java VM. PPPJ 2015: 170-181 - 2014
- [c53]George Nagy, Sharad C. Seth, David W. Embley:
End-to-End Conversion of HTML Tables for Populating a Relational Database. Document Analysis Systems 2014: 222-226 - [c52]David W. Embley, Sharad C. Seth, George Nagy:
Transforming Web Tables to a Relational Database. ICPR 2014: 2781-2786 - 2013
- [c51]Sharad C. Seth, George Nagy:
Segmenting Tables via Indexing of Value Cells by Table Headers. ICDAR 2013: 887-891 - 2012
- [c50]Dongyuan Zhan, Hong Jiang, Sharad C. Seth:
Locality & utility co-optimization for practical capacity management of shared last level caches. ICS 2012: 279-290 - 2011
- [c49]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. Asian Test Symposium 2011: 297-302 - [c48]George Nagy, Sharad C. Seth, Dongpu Jin, David W. Embley, Spencer Machado, Mukkai S. Krishnamoorthy:
Data Extraction from Web Tables: The Devil is in the Details. ICDAR 2011: 242-246 - [c47]David W. Embley, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth:
Factoring Web Tables. IEA/AIE (1) 2011: 253-263 - 2010
- [c46]Sharad C. Seth, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy:
Analysis and taxonomy of column header categories for web tables. Document Analysis Systems 2010: 81-88 - [c45]Dongyuan Zhan, Hong Jiang, Sharad C. Seth:
Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching. IPDPS 2010: 1-10 - [c44]Nathan Schemm, Sina Balkir, Sharad C. Seth:
Hardware implementation of the double-tree scan architecture. ISCAS 2010: 429-432 - [c43]Dongyuan Zhan, Hong Jiang, Sharad C. Seth:
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches. MICRO 2010: 163-174 - [c42]Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya:
A Unified Solution to Scan Test Volume, Time, and Power Minimization. VLSI Design 2010: 9-14 - [c41]Zhen Chen, Sharad C. Seth, Dong Xiang:
A novel hybrid delay testing scheme with low test power, volume, and time. VTS 2010: 307-312 - 2009
- [c40]Raghav Krishna Padmanabhan, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, William Silversmith:
Interactive Conversion of Web Tables. GREC 2009: 25-36 - [c39]Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Raghav K. Padmanabhan, Sharad C. Seth, William Silversmith:
From Tessellations to Table Interpretation. Calculemus/MKM 2009: 422-437 - 2008
- [c38]Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram:
Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241 - 2007
- [c37]Jian Kang, Sharad C. Seth, Shashank K. Mehta:
Symbolic Path Sensitization Analysis and Applications. ATS 2007: 439-444 - [c36]Jian Kang, Sharad C. Seth, Vijay Gangaram:
Efficient RTL Coverage Metric for Functional Test Selection. VTS 2007: 318-324 - 2006
- [c35]Ashutosh Joshi, George Nagy, Daniel P. Lopresti, Sharad C. Seth:
A Maximum-Likelihood Approach to Symbolic Indirect Correlation. ICPR (3) 2006: 99-103 - [c34]Daniel P. Lopresti, George Nagy, Sharad C. Seth, Xiaoli Zhang:
Multi-character Field Recognition for Arabic and Chinese Handwriting. SACH 2006: 218-230 - 2005
- [c33]Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya:
Efficient Test Compaction for Pseudo-Random Testing. Asian Test Symposium 2005: 337-342 - [c32]Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya:
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. VLSI Design 2005: 491-496 - 2004
- [c31]George Nagy, Ashutosh Joshi, Mukkai S. Krishnamoorthy, Yu Lin, Daniel P. Lopresti, Shashank K. Mehta, Sharad C. Seth:
A nonparametric classifier for unsegmented text. DRR 2004: 102-108 - 2003
- [c30]George Nagy, Sharad C. Seth, Shashank K. Mehta, Yu Lin:
Indirect Symbolic Correlation Approach to Unsegmented Text Recognition. CVPR Workshops 2003: 22 - [c29]Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang:
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. ITC 2003: 470-479 - [c28]Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang:
Low-Energy BIST Design for Scan-based Logic Circuits. VLSI Design 2003: 546-551 - 2002
- [c27]Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
A Novel Method to Improve the Test Efficiency of VLSI Tests. ASP-DAC/VLSI Design 2002: 499-504 - 2001
- [c26]Don Sylwester, Sharad C. Seth:
Adaptive Segmentation of Document Images. ICDAR 2001: 827-831 - [c25]Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr:
Design Verification and Functional Testing of FiniteState Machines. VLSI Design 2001: 189-195 - 2000
- [c24]Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr:
Exploiting don't cares to enhance functional tests. ITC 2000: 538-546 - 1999
- [c23]Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu:
Cooperative Text and Line-Art Extraction from a Topographic Map. ICDAR 1999: 467-470 - [c22]Shashank K. Mehta, Sharad C. Seth:
Empirical Computation of Reject Ratio in VLSI Testing. VLSI Design 1999: 506-511 - 1998
- [c21]Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472- - [c20]Vishwani D. Agrawal, Sharad C. Seth:
Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312 - 1997
- [c19]George Nagy, Ashok Samal, Sharad C. Seth, T. Fisher, E. Guthmann, K. Kalafala, Luyang Li, Prateek Sarkar, S. Sivasubramaniam, Yihong Xu:
A Prototype for Adaptive Association of Street Names with Streets on Maps. GREC 1997: 302-313 - [c18]Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth:
Synthesis for Testability by Two-Clock Control. VLSI Design 1997: 279-283 - 1996
- [c17]Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293 - 1995
- [c16]Stephen D. Scott, Ashok Samal, Sharad C. Seth:
HGA: A Hardware-Based Genetic Algorithm. FPGA 1995: 53-59 - [c15]Don Sylwester, Sharad C. Seth:
A trainable, single-pass algorithm for column segmentation. ICDAR 1995: 615-618 - [c14]Yuhong Yu, Ashok Samal, Sharad C. Seth:
A system for recognizing a large class of engineering drawings. ICDAR 1995: 791-794 - [c13]Sivaramakrishnan Venkatraman, Sharad C. Seth, Prathima Agrawal:
Parallel test generation with low communication overhead. VLSI Design 1995: 116-120 - 1994
- [c12]Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester:
Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. VLSI Design 1994: 29-32 - 1993
- [c11]Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Clock partitioning for testability. Great Lakes Symposium on VLSI 1993: 42-46 - 1992
- [c10]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. EURO-DAC 1992: 138-141 - [c9]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. VLSI Design 1992: 4-11 - [c8]Kent L. Einspahr, Sharad C. Seth:
A Switch-Level Test Generation System. VLSI Design 1992: 43-48 - 1991
- [c7]Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal:
Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217 - 1990
- [c6]Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal:
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720 - [c5]Paul Kenyon, Prathima Agrawal, Sharad C. Seth:
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. MICRO 1990: 97-106 - 1989
- [c4]Raghu V. Hudli, Sharad C. Seth:
Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. ITC 1989: 364-372 - 1988
- [c3]Wuudiann Ke, Sharad C. Seth, Bhargab B. Bhattacharya:
A fast fault simulation algorithm for combinational circuits. ICCAD 1988: 166-169 - 1985
- [c2]Sharad C. Seth:
Predicting Fault Coverage from Probabilistic Testability. ITC 1985: 803-807 - 1981
- [c1]Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal:
LSI product quality and fault coverage. DAC 1981: 196-203
Reference Works
- 2017
- [r4]Sharad C. Seth, Ashok Samal:
Conflation of Features. Encyclopedia of GIS 2017: 291-297 - [r3]Ashok Samal, Sharad C. Seth:
Feature Extraction, Abstract. Encyclopedia of GIS 2017: 602-611 - 2008
- [r2]Sharad C. Seth, Ashok Samal:
Conflation of Features. Encyclopedia of GIS 2008: 129-133 - [r1]Ashok Samal, Sharad C. Seth:
Feature Extraction, Abstract. Encyclopedia of GIS 2008: 314-320
Coauthor Index
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