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Journal Articles
- 2015
[j11]Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler:
IBM POWER8 processor core microarchitecture. IBM J. Res. Dev. 59(1) (2015)- [j10]Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block:
Advanced features in IBM POWER8 systems. IBM J. Res. Dev. 59(1) (2015) - 2013
- [j9]Vijayshankar Raman, Gopi K. Attaluri, Ronald Barber, Naresh Chainani, David Kalmuk, Vincent KulandaiSamy, Jens Leenstra, Sam Lightstone, Shaorong Liu, Guy M. Lohman, Tim Malkemus, René Müller, Ippokratis Pandis, Berni Schiefer, David Sharpe, Richard Sidle, Adam J. Storm, Liping Zhang:
DB2 with BLU Acceleration: So Much More than Just a Column Store. Proc. VLDB Endow. 6(11): 1080-1091 (2013) - 2011
- [j8]Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits 46(1): 145-161 (2011) - 2007
- [j7]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - [j6]Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough:
IBM POWER6 accelerators: VMX and DFU. IBM J. Res. Dev. 51(6): 663-684 (2007) - [j5]Joachim Fenkes, Tobias Gemmeke
, Jens Leenstra:
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. J. Low Power Electron. 3(1): 54-59 (2007) - 2006
- [j4]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - 2001
- [j3]Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel:
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core. IEEE J. Solid State Circuits 36(11): 1628-1635 (2001) - 2000
- [j2]David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. 44(6): 799-822 (2000) - 1989
- [j1]Gerhard Roos, Jens Leenstra, Thomas Schwederski, Lambert Spaanenburg, Bernd Höfflinger:
On structured gate forest VLSI design. Microprocessing and Microprogramming 27(1-5): 785-792 (1989)
Conference and Workshop Papers
- 2014
- [c12]Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban:
POWER8 design methodology innovations for improving productivity and reducing power. CICC 2014: 1-9 - 2008
- [c11]Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding:
Scan chain clustering for test power reduction. DAC 2008: 828-833 - 2007
- [c10]Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
Scan Test Planning for Power Reduction. DAC 2007: 521-526 - 2006
- [c9]Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum 2006: 244-248 - [c8]Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. ITC 2006: 1-8 - 2005
- [c7]Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor. ESSCIRC 2005: 203-206 - 2001
- [c6]Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469 - 1997
- [c5]Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile:
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. DAC 1997: 89-94 - 1991
- [c4]Jens Leenstra, Lambert Spaanenburg:
Hierarchical Test Program Development for Scan Testable Circuits. ITC 1991: 375-384 - 1990
- [c3]Jens Leenstra, Lambert Spaanenburg:
Hierarchical test assembly for macro based VLSI design. ITC 1990: 520-529 - 1989
- [c2]Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg:
Issues in the test of artificial neural networks. ICCD 1989: 487-490 - [c1]Jens Leenstra, Lambert Spaanenburg:
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. ITC 1989: 838-845
Coauthor Index
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