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Junyoung Song
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2020 – today
- 2024
- [j21]Hyunsu Park, Seung-Myeong Yu, Junyoung Song:
An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces. IEEE Access 12: 145934-145943 (2024) - [j20]Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song:
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1169-1172 (2024) - 2023
- [c16]Gwangmyeong An, Juneho Yoon, Taeho Kim, Hyunsu Jang, Myeongju Park, Bongsu Kim, Jongchan An, Junyoung Song:
A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator. ISOCC 2023: 19-20 - 2022
- [j19]Minseob Shim, Junwon Jeong, Junyoung Song, Yongtae Kim, Woong Choi:
Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 5104-5108 (2022) - [c15]Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC 2022: 1-3 - 2021
- [j18]Yunha Kang, Junyoung Song:
A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process. IEICE Electron. Express 18(18): 20210253 (2021) - [j17]Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim:
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits 56(2): 581-590 (2021) - [j16]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1567-1574 (2021) - [c14]Yunha Kang, Seung-Myeong Yu, Jongchan An, Wooyoung Choi, Junyoung Song:
A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process. ICEIC 2021: 1-4 - [c13]Seung-Myeong Yu, Yunha Kang, Wooyoung Choi, Jongchan An, Junyoung Song:
A 20Gb/s/pin Single-ended Transmitter with FEXT Compensation Technique. ICEIC 2021: 1-3 - [c12]Wooyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song:
Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control. ISOCC 2021: 79-80 - [c11]Yunha Kang, Junyoung Song:
A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS. ISOCC 2021: 155-156
2010 – 2019
- 2019
- [j15]Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. IEEE J. Solid State Circuits 54(2): 463-475 (2019) - [j14]Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 192-196 (2019) - [j13]Junyoung Song, Yongtae Kim, Chulwoo Kim:
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1982-1986 (2019) - [c10]Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim:
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC 2019: 382-384 - 2018
- [j12]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 331-342 (2018) - 2017
- [j11]Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim:
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 650-654 (2017) - [j10]Jungtaek You, Junyoung Song, Chulwoo Kim:
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1207-1211 (2017) - [j9]Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim:
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2691-2702 (2017) - [j8]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim:
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 344-353 (2017) - [c9]Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim:
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. ISSCC 2017: 490-491 - 2016
- [j7]Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1092-1103 (2016) - [j6]Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2768-2777 (2016) - [c8]Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim:
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. VLSI Circuits 2016: 1-2 - 2015
- [c7]Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim:
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. ISSCC 2015: 1-3 - 2014
- [b1]Chulwoo Kim, Hyun-Woo Lee, Junyoung Song:
High-Bandwidth Memory Interface. Springer Briefs in Electrical and Computer Engineering, Springer 2014, ISBN 978-3-319-02380-9, pp. i-viii, 1-88 - [j5]Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim:
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 865-869 (2014) - [j4]Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim:
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2156-2163 (2014) - [c6]Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong:
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC 2014: 434-435 - 2013
- [j3]Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim:
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. IEEE J. Solid State Circuits 48(3): 711-723 (2013) - [j2]Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim:
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 268-278 (2013) - [j1]Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim:
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 173-177 (2013) - [c5]Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim:
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. ASP-DAC 2013: 89-90 - [c4]Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim:
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. ISSCC 2013: 312-313 - 2012
- [c3]Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim:
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS. ISCAS 2012: 1959-1962 - [c2]Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim:
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. ISSCC 2012: 48-50
2000 – 2009
- 2009
- [c1]Jabeom Koo, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. CICC 2009: 717-720
Coauthor Index
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last updated on 2024-11-07 20:32 CET by the dblp team
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