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ORCIDASP-DAC 2013: Yokohama, Japan
- 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. IEEE 2013, ISBN 978-1-4673-3029-9
- A. Ege Engin
:
Equivalent circuit model extraction for interconnects in 3D ICs. 1-6 - Tadatoshi Sekine, Hideki Asai:
Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. 7-12 - Joohee Kim, Joungho Kim:
Signal integrity modeling and measurement of TSV in 3D IC. 13-16 - Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu:
Power distribution network modeling for 3-D ICs with TSV arrays. 17-22 - Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. 23-28 - Jinho Lee, Dongwook Lee, Sunwook Kim, Kiyoung Choi:
Deflection routing in 3D Network-on-Chip with TSV serialization. 29-34 - Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Farhad Mehdipour:
MD: Minimal path-based fault-tolerant routing in on-Chip Networks. 35-40 - Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin:
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC. 41-46 - Mohammed El-Shambakey, Binoy Ravindran:
On real-time STM concurrency control for embedded software with improved schedulability. 47-52 - Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty:
Schedule integration for time-triggered systems. 53-58 - Donghwa Shin, Kitae Kim, Naehyuck Chang, Woojoo Lee, Yanzhi Wang, Qing Xie, Massoud Pedram:
Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics. 59-64 - Yazhi Huang, Mengying Zhao, Chun Jason Xue:
WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems. 65-70 - Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. 71-72 - Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto:
A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. 73-74 - Tadayoshi Enomoto, Nobuaki Kobayashi:
A low power multimedia processor implementing dynamic voltage and frequency scaling technique. 75-76 - Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. 77-78 - Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. 79-80 - Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi:
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. 81-82 - Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi:
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. 83-84 - Youngjoo Lee, Hoyoung Yoo, In-Cheol Park:
A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process. 85-86 - Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto:
A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. 87-88 - Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim:
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. 89-90 - Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. 91-92 - Shunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS. 93-94 - Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa:
A full 4-channel 60 GHz direct-conversion transceiver. 95-96 - Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. 97-98 - Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa:
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. 99-100 - Kenta Sogo, Akihiro Toya, Takamaro Kikkawa:
A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. 101-102 - Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges. 103-104 - Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera:
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. 105-106 - Jungmoon Kim, Chulwoo Kim:
A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting. 107-108 - Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. 109-110 - Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. 111-112 - Jörg Henkel, Thomas Ebi, Hussam Amrouch, Heba Khdr:
Thermal management for dependable on-chip systems. 113-118 - Hidetoshi Onodera:
Dependable VLSI Platform using Robust Fabrics. 119-124 - Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Luis Angel D. Bathen, Mark Gottscho:
Variability-aware memory management for nanoscale computing. 125-132 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. 133-138 - Chen Wang, Weikang Qian:
Optimizing multi-level combinational circuits for generating random bits. 139-144 - Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler:
Improving the mapping of reversible circuits to quantum circuits using multiple target lines. 145-150 - Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai:
I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. 151-156 - Zao Liu, Sheldon X.-D. Tan, Hai Wang, Sahana Swarup, Ashish Gupta:
Compact nonlinear thermal modeling of packaged integrated systems. 157-162 - Wei Zhao, Yici Cai, Jianlei Yang:
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. 163-168 - Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
Realization of frequency-domain circuit analysis through random walk. 169-174 - Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen:
A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. 175-180 - Pei-Ci Wu, Qiang Ma, Martin D. F. Wong:
An ILP-based automatic bus planner for dense PCBs. 181-186 - Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng:
Layer minimization in escape routing for staggered-pin-array PCBs. 187-192 - Pei-Ci Wu, Martin D. F. Wong:
Network flow modeling for escape routing on staggered pin arrays. 193-198 - Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi:
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. 199-204 - Wajid Hassan Minhass, Paul Pop, Jan Madsen, Tsung-Yi Ho:
Control synthesis for the flow-based microfluidic large-scale integration biochips. 205-212 - Kai-Han Tseng, Sheng-Chi You, Wajid Hassan Minhass, Tsung-Yi Ho, Paul Pop:
A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips. 213-218 - Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk:
Design and verification tools for continuous fluid flow-based microfluidic devices. 219-224 - Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang:
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications. 225-230 - Haris Javaid, Daniel Witono, Sri Parameswaran:
Multi-mode pipelined MPSoCs for streaming applications. 231-236 - Cong Hao, Song Chen, Takeshi Yoshimura:
Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis. 237-242 - Yuko Hara-Azumi, Takuya Azumi, Nikil D. Dutt:
VISA synthesis: Variation-aware Instruction Set Architecture synthesis. 243-248 - Bei Yu, Jhih-Rong Gao, David Z. Pan:
L-shape based layout fracturing for e-beam lithography. 249-254 - Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. 255-260 - Yuelin Du, Hongbo Zhang, Qiang Ma, Martin D. F. Wong:
Linear time algorithm to find all relocation positions for EUV defect mitigation. 261-266 - Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi:
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control. 267-272 - Qing'an Li, Jianhua Li, Liang Shi, Chun Jason Xue, Yiran Chen, Yanxiang He:
Compiler-assisted refresh minimization for volatile STT-RAM cache. 273-278 - Duo Liu, Tianzheng Wang, Yi Wang, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems. 279-284 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches. 285-290 - Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen:
Loadsa: A yield-driven top-down design method for STT-RAM array. 291-296 - Doris Chen, Deshanand P. Singh:
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. 297-304 - Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen:
High-level synthesis of multiple dependent CUDA kernels on FPGA. 305-312 - Perry Cheng, Stephen J. Fink, Rodric M. Rabbah, Sunil Shukla:
The Liquid Metal IP bridge. 313-319 - Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo:
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. 320-325 - Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Zili Shao:
Optimizing translation information management in NAND flash memory storage systems. 326-331 - Xianglei Dang, Xiaoyin Wang, Dong Tong, Zichao Xie, Lingda Li, Keyi Wang:
An adaptive filtering mechanism for energy efficient data prefetching. 332-337 - Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. 338-343 - Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath:
Optimization of overdrive signoff. 344-349 - Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. 350-355 - Sangmin Kim, Duckhwan Kim, Youngsoo Shin:
Pulsed-latch ASIC synthesis in industrial design flow. 356-361 - Kan Wang, Sheqin Dong:
Power optimization for application-specific 3D network-on-chip with multiple supply voltages. 362-367 - Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki:
Hardware security strategies exploiting nanoelectronic circuits. 368-372 - Mian Dong, Po-Hsiang Lai, Zhu Li:
Can we identify smartphone app by power trace? [Extended abstract for special session]. 373-375 - Jiwu Shu, Zhirong Shen, Wei Xue, Yingxun Fu:
Secure storage system and key technologies. 376-383 - Kent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen, Kang Li:
Mobile user classification and authorization based on gesture usage recognition. 384-389 - Kazuya Masu, Noboru Ishihara, Toshifumi Konishi, Katsuyuki Machida, Hiroshi Toshiyoshi:
Challenges in integration of diverse functionalities on CMOS. 390-393 - Frank Lee, Bill Shen, Willy Chen, Suk Lee:
3DIC from concept to reality. 394-398 - Shinya Tokunaga:
2.5D design methodology. 399-402 - Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne:
Design issues in heterogeneous 3D/2.5D integration. 403-410 - Matthias Kauer, Sebastian Steinhorst, Dip Goswami, Reinhard Schneider, Martin Lukasiewycz, Samarjit Chakraborty:
Formal verification of distributed controllers using Time-Stamped Event Count Automata. 411-416 - Sebastian Reiter, Michael Pressler, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
Reliability assessment of safety-relevant automotive systems in a model-based design flow. 417-422 - Hehua Zhang, Yu Jiang, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun:
Sequential dependency and reliability analysis of embedded systems. 423-428 - Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu:
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. 429-434 - Kai-Chung Chan, Chao-Jam Hsu, Jia-Ming Lin:
A flexible fixed-outline floorplanning methodology for mixed-size modules. 435-440 - Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao:
Optimizing routability in large-scale mixed-size placement. 441-446 - Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao:
Symmetrical buffered clock-tree synthesis with supply-voltage alignment. 447-452 - Stefan Hougardy, Tim Nieberg, Jan Schneider:
BonnCell: Automatic layout of leaf cells. 453-460 - Yun Liang, Zheng Cui, Kyle Rupnow, Deming Chen:
Register and thread structure optimization for GPUs. 461-466 - Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, Heiko Falk:
Real-time partitioned scheduling on multi-core systems with local and global memories. 467-472 - Zao Liu, Tailong Xu, Sheldon X.-D. Tan, Hai Wang:
Dynamic thermal management for multi-core microprocessors considering transient thermal effects. 473-478 - Mohammad H. Foroozannejad, Brent Bohnenstiehl, Soheil Ghiasi:
BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms. 479-484 - Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu:
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. 485-490 - Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho:
A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration. 491-496 - Yang Ge, Yukan Zhang, Qinru Qiu:
Improving energy efficiency for energy harvesting embedded systems. 497-502 - Arne Heittmann, Tobias G. Noll:
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation. 503-508 - Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang:
HS3DPG: Hierarchical simulation for 3D P/G network. 509-514 - Yang Zhang, Neric Fong, Ngai Wong:
Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation. 515-520 - Li Yu, Omar Mysore, Lan Wei, Luca Daniel, Dimitri A. Antoniadis, Ibrahim M. Elfadel, Duane S. Boning:
An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits. 521-526 - Andrew B. Kahng, Siddhartha Nath, Tajana Rosing:
On potential design impacts of electromigration awareness. 527-532 - Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker:
Provably optimal test cube generation using quantified boolean formula solving. 533-539 - Louis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen:
Synthesizing multiple scan chains by cost-driven spectral ordering. 540-545 - Yuki Yoshikawa:
A binding algorithm in high-level synthesis for path delay testability. 546-551 - Baris Arslan, Alex Orailoglu:
Full exploitation of process variation space for continuous delivery of optimal delay test quality. 552-557 - Koji Inoue:
SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs. 558-560 - Masaaki Kondo, Son Truong Nguyen, Tomoya Hirao, Takeshi Soga, Hiroshi Sasaki, Koji Inoue:
SMYLEref: A reference architecture for manycore-processor SoCs. 561-564 - Hiroyuki Tomiyama, Takuji Hieda, Naoki Nishiyama, Noriko Etani, Ittetsu Taniguchi:
SMYLE OpenCL: A programming framework for embedded many-core SoCs. 565-567 - Yuri Ardila, Natsuki Kawai, Takashi Nakamura, Yosuke Tamura:
Support tools for porting legacy applications to multicore. 568-573 - Yukoh Matsumoto, Hiroyuki Uchida, Michiya Hagimoto, Yasumori Hibi, Sunao Torii, Masamichi Izumida:
Manycore processor for video mining applications. 574-575 - Mian Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel:
Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization. 576-581 - Su Myat Min, Haris Javaid, Sri Parameswaran:
RExCache: Rapid exploration of unified last-level cache. 582-587 - Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang:
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. 588-593 - Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Statistical analysis of BTI in the presence of process-induced voltage and temperature variations. 594-600 - Mojtaba Ebrahimi, Liang Chen, Hossein Asadi, Mehdi Baradaran Tahoori:
CLASS: Combined logic and architectural soft error sensitivity analysis. 601-607 - Tun Li, Dan Zhu, Sikun Li, Yang Guo:
Application specified soft error failure rate analysis using sequential equivalence checking techniques. 608-613 - Michihiro Shintani, Takashi Sato:
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. 614-619 - Jude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa:
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. 620-625 - Yu Zheng, Aswin Raghav Krishna, Swarup Bhunia:
ScanPUF: Robust ultralow-overhead PUF using scan chain. 626-631 - Ting-Shuo Chou, Tony Givargis, Chen Huang, Bailey Miller, Frank Vahid:
An efficient compression scheme for checkpointing of FPGA-based digital mockups. 632-637 - Di Zhu, Yanzhi Wang, Siyu Yue, Qing Xie, Massoud Pedram, Naehyuck Chang:
Maximizing return on investment of a grid-connected hybrid electrical energy storage system. 638-643 - Peter De Dobbelaere:
Silicon photonics technology platform for embedded and integrated optical interconnect systems. 644-647 - Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita:
High-frequency circuit design for 25 Gb/s×4 optical transceiver. 648-651 - Shigeru Nakamura:
Design and application of highly integrated optical switches based on silicon photonics. 652-654 - Junichi Fujikata, Masataka Noguchi, Makoto Miura, Masashi Takahashi, Shigeki Takahashi, Tsuyoshi Horikawa, Yutaka Urino, Takahiro Nakamura, Yasuhiko Arakawa:
High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence system. 655-656 - Daniel W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, Nam Sung Kim, Michael J. Schulte:
Reevaluating the latency claims of 3D stacked memories. 657-662 - Le-Nguyen Tran, Fadi J. Kurdahi, Ahmed M. Eltawil, Houman Homayoun:
Heterogeneous memory management for 3D-DRAM and external DRAM with QoS. 663-668 - Keitarou Oka, Hiroshi Sasaki, Koji Inoue:
Line sharing cache: Exploring cache capacity with frequent line value locality. 669-674 - Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King:
ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise. 675-680 - Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
High-density integration of functional modules using monolithic 3D-IC technology. 681-686 - Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim:
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. 687-692 - Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan, Xin Zhao, Sung Kyu Lim:
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. 693-698 - Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang:
Stacking signal TSV for thermal dissipation in global routing for 3D IC. 699-704 - Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong:
VFCC: A verification framework of cache coherence using parallel simulation. 705-710 - Bernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
A computational model for SAT-based verification of hardware-dependent low-level embedded system software. 711-716 - Bao Le, Dipanjan Sengupta, Andreas G. Veneris:
Reviving erroneous stability-based clock-gating using partial Max-SAT. 717-722 - Bin Xue, Prosenjit Chatterjee, Sandeep K. Shukla:
Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models. 723-728 - Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software. 729-734 - Huping Ding, Yun Liang, Tulika Mitra:
Shared cache aware task mapping for WCRT minimization. 735-740 - Qing Wan, Hui Wu, Jingling Xue:
Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor. 741-748 - Qing Xie, Di Zhu, Yanzhi Wang, Massoud Pedram, Younghyun Kim, Naehyuck Chang:
An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems. 749-754 - Yang Song, Haipeng Fu, Hao Yu, Guoyong Shi:
Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter. 755-760 - Xuexin Liu, Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle, Yici Cai:
Performance bound and yield analysis for analog circuits under process variations. 761-766 - Muhammad Umer Farooq, Likun Xia:
Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomials. 767-772 - Marcel Gort, Jason Helge Anderson:
Range and bitmask analysis for hardware optimization in high-level synthesis. 773-779 - Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang:
A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis. 780-786 - Nikhil A. Patil, Derek Chiou:
Implementing microprocessors from simplified descriptions. 787-793 - Mirela Alistar, Paul Pop, Jan Madsen:
Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips. 794-800
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