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ORCIDPhilippe Magarshack
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2010 – 2019
- 2015
[c17]Philippe Magarshack:
Breakthrough technologies and reference designs for new IoT applications. VLSIC 2015: 42-- 2014
- [j4]David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack:
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. IEEE J. Solid State Circuits 49(4): 812-826 (2014) - [c16]Marco Casale-Rossi, Giovanni De Micheli, Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack:
Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads? DATE 2014: 1-4 - [c15]Robin Wilson, Edith Beigné
, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack:
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c14]Philippe Magarshack, Philippe Flatresse, Giorgio Cesana:
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. DATE 2013: 952-957 - 2012
- [c13]Philippe Magarshack, Andreia Cathelin:
Gaining 10x in energy efficiency in the next decade in consumer products. VLSI-DAT 2012: 1-2 - 2011
- [c12]Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31 - 2010
- [c11]Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic:
3-D stacked die: now or future? DAC 2010: 298-299
2000 – 2009
- 2009
- [j3]Jean-Pierre Schoellkopf, Philippe Magarshack:
Low-Power Design Solutions forWireless Multimedia SoCs. IEEE Des. Test Comput. 26(2): 20-29 (2009) - 2007
- [c10]Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki:
DFM/DFY: should you trust the surgeon or the family doctor? DATE 2007: 439-442 - [c9]Philippe Magarshack:
Design challenges in 45nm and below: DFM, low-power and design for reliability. ACM Great Lakes Symposium on VLSI 2007: 1 - 2006
- [c8]Gadi Singer, Philippe Magarshack, Dennis Buss, Fu-Chieh Hsu, Ho-Kyu Kang:
"The IC nanometer race -- what will it take to win?". DAC 2006: 77-78 - 2004
- [j2]Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack:
Guest Editors' Introduction: Design for Yield and Reliability. IEEE Des. Test Comput. 21(3): 177-182 (2004) - 2003
- [c7]Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi:
Fast, cheap and under control: the next implementation fabric. DAC 2003: 354-355 - [c6]Philippe Magarshack, Pierre G. Paulin:
System-on-chip beyond the nanometer wall. DAC 2003: 419-424 - [c5]Philippe Magarshack:
Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies. VTS 2003: 4 - 2002
- [j1]Philippe Magarshack:
Improving SoC Design Quality through a Reproducible Design Flow. IEEE Des. Test Comput. 19(1): 76-83 (2002) - [c4]Philippe Magarshack:
Systems-on-chip needs for embedded software development: an industrial perspective. LCTES-SCOPES 2002: 1 - [c3]Philippe Magarshack:
SoC's Trends and Challenges going to 0.10µm. MTDT 2002 - 2001
- [c2]Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang:
Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? DAC 2001: 419 - [c1]Philippe Magarshack:
Quality of SoC Designs through Quality of the Design Flow: Status and Needs. ISQED 2001: 241-
Coauthor Index
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