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ORCIDISPD 2010: San Francisco, California, USA
- Prashant Saxena, Yao-Wen Chang:
Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010. ACM 2010, ISBN 978-1-60558-920-6 - Louis Scheffer:
Physical design of biological systems. 1
Modern physical design challenges
- Patrick Groeneveld:
Going with the flow: bridging the gap between theory and practice in physical design. 3 - Neeraj Kaul:
Design planning trends and challenges. 5 - Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam
, Jarrod A. Roy, Gustavo E. Téllez:
What makes a design difficult to route. 7-12 - Sani R. Nassif, Kevin J. Nowka:
Physical design challenges beyond the 22nm node. 13-14 - Serge Leef:
Challenges and opportunities in optimization of automotive electronics. 15
Advances in routing
- John Park:
Thinking outside of the chip. 17 - Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
B-escape: a simultaneous escape routing algorithm based on boundary routing. 19-25 - Gaurav Ajwani, Chris Chu, Wai-Kei Mak:
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. 27-34 - Jin Hu, Jarrod A. Roy, Igor L. Markov:
Completing high-quality global routes. 35-41
Analog design automation
- Rob A. Rutenbar:
Analog layout synthesis: what's missing? 43 - Mar Hershenson:
Design platform for electrical and physical co-design of analog circuits. 45 - Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann:
Automatic generation of hierarchical placement rules for analog integrated circuits. 47-54
Physical design for 3D
- Sachin S. Sapatnekar:
Adding a new dimension to physical design. 55 - Vassilios Gerousis:
Physical design implementation for 3D IC: methodology and tools. 57 - Zongwu Tang:
Efficient design practices for thermal management of a TSV based 3D IC system. 59 - Jason Cong, Guojie Luo:
An analytical placer for mixed-size 3D placement. 61-66
Physical synthesis
- Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho:
Logical and physical restructuring of fan-in trees. 67-74 - Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. 75-82 - Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. 83-90 - Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. 91-96
Design for manufacturing
- Yaoguang Wei, Sachin S. Sapatnekar:
Dummy fill optimization for enhanced manufacturability. 97-104 - Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang:
Density gradient minimization with coupling-constrained dummy fill for CMP control. 105-111 - Yongchan Ban, Savithri Sundareswaran, David Z. Pan:
Total sensitivity based dfm optimization of standard library cells. 113-120 - Yue Xu, Chris Chu:
A matching based decomposer for double patterning lithography. 121-126
Advances in clock tree designs and ISPD'10 clock synthesis contest
- Ashutosh Chakraborty, David Z. Pan:
Skew management of NBTI impacted gated clock trees. 127-133 - Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li:
Accurate clock mesh sizing via sequential quadraticprogramming. 135-142 - Cliff C. N. Sze:
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. 143
Performance and reliability optimization
- Rupesh S. Shelar, Marek Patyra:
Impact of local interconnects on timing and power in a high performance microprocessor. 145-152 - Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. 153-160 - Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
Performance study of VeSFET-based, high-density regular circuits. 161-168 - Yufu Zhang, Bing Shi, Ankur Srivastava:
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems. 169-176 - Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. 177-184
Clustering and biochip placement & routing
- Jackey Z. Yan, Chris Chu, Wai-Kei Mak:
SafeChoice: a novel clustering algorithm for wirelength-driven placement. 185-192 - Zigang Xiao, Evangeline F. Y. Young:
Droplet-routing-aware module placement for cross-referencing biochips. 193-199 - Tsung-Wei Huang, Tsung-Yi Ho:
A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. 201-208
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