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ORCIDYun Chiu
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- affiliation: University of Texas at Dallas, Texas Analog Center of Excellence, Richardson, TX, USA
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2020 – today
- 2022
[j33]Yanqing Li
, Yun Chiu:
An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 4639-4643 (2022)- 2021
- [j32]Yun Chiu, Man-Kay Law, Nagendra Krishnapura, Jason T. Stauth, Jeffrey S. Walling:
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 56(12): 3547-3550 (2021) - 2020
- [j31]Yanqing Li, Yuan Zhou, Yun Chiu:
A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits. IEEE Trans. Circuits Syst. 67-II(11): 2327-2331 (2020)
2010 – 2019
- 2019
- [j30]Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 441-451 (2019) - [j29]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. IEEE J. Solid State Circuits 54(8): 2207-2218 (2019) - 2018
- [j28]Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS. IEEE J. Solid State Circuits 53(3): 839-849 (2018) - [j27]Shuang Zhu, Bo Wu, Yongda Cai, Yun Chiu:
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS. IEEE J. Solid State Circuits 53(4): 1172-1183 (2018) - 2017
- [j26]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS. IEEE J. Solid State Circuits 52(4): 1091-1100 (2017) - [j25]Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer. IEEE J. Solid State Circuits 52(6): 1551-1562 (2017) - [j24]Hai Huang, Hongda Xu, Brian Elies, Yun Chiu:
A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation. IEEE J. Solid State Circuits 52(12): 3235-3247 (2017) - [c26]Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu:
28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. ISSCC 2017: 472-473 - [c25]Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. ISSCC 2017: 476-477 - [c24]Sudipta Sarkar, Benwei Xu, Brian Elies, Yun Chiu:
An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration. MWSCAS 2017: 591-594 - 2016
- [j23]Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu:
A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM. IEEE J. Solid State Circuits 51(8): 1785-1796 (2016) - [j22]Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu:
A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR. IEEE J. Solid State Circuits 51(12): 2893-2905 (2016) - [c23]Shuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu:
A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices. ISQED 2016: 450-455 - [c22]Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu:
15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS. ISSCC 2016: 270-271 - [c21]Benwei Xu, Yuan Zhou, Yun Chiu:
A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j21]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector. IEEE J. Solid State Circuits 50(4): 920-931 (2015) - [j20]Bo Wu, Yun Chiu:
A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3. IEEE J. Solid State Circuits 50(8): 1772-1784 (2015) - [j19]Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu:
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 654-661 (2015) - [j18]Benwei Xu, Yun Chiu:
Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1306-1314 (2015) - [c20]Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer. A-SSCC 2015: 1-4 - [c19]Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu:
A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM. CICC 2015: 1-4 - 2014
- [j17]Seung-Chul Lee, Yun Chiu:
A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR. IEEE J. Solid State Circuits 49(3): 695-707 (2014) - [j16]Guanhua Wang, Foti Kacani, Yun Chiu:
IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 11-15 (2014) - [c18]Bo Wu, Yun Chiu:
An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS. CICC 2014: 1-4 - [c17]Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu:
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system. CICC 2014: 1-4 - [c16]Sudipta Sarkar, Yuan Zhou, Yun Chiu:
PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy. MWSCAS 2014: 1049-1052 - [c15]Yuan Zhou, Benwei Xu, Yun Chiu:
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. VLSIC 2014: 1-2 - 2013
- [c14]Guanhua Wang, Yun Chiu:
Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering. CICC 2013: 1-4 - [c13]Benwei Xu, Yun Chiu:
Background calibration of time-interleaved ADC using direct derivative information. ISCAS 2013: 2456-2459 - [c12]Yuan Zhou, Yun Chiu:
Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC. MWSCAS 2013: 677-680 - 2012
- [j15]Wenbo Liu, Yun Chiu:
Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1384-1395 (2012) - [j14]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 564-568 (2012) - [c11]Wenbo Liu, Pingli Huang, Yun Chiu:
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. CICC 2012: 1-4 - [c10]Seung-Chul Lee, Brian Elies, Yun Chiu:
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration. VLSIC 2012: 164-165 - 2011
- [j13]Yun Chiu:
Equalization techniques for nonlinear analog circuits. IEEE Commun. Mag. 49(4): 132-139 (2011) - [j12]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. IEEE J. Solid State Circuits 46(8): 1893-1903 (2011) - [j11]Wenbo Liu, Pingli Huang, Yun Chiu:
A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration. IEEE J. Solid State Circuits 46(11): 2661-2672 (2011) - [j10]Seung-Chul Lee, Yun Chiu:
Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 690-698 (2011) - 2010
- [j9]Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu:
Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier. IEEE J. Solid State Circuits 45(8): 1602-1614 (2010) - [j8]Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon:
A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling. IEEE J. Solid State Circuits 45(11): 2262-2272 (2010) - [j7]Seung-Chul Lee, Yun Chiu:
Digital Calibration of Nonlinear Memory Errors in Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2462-2475 (2010) - [j6]Bei Peng, Hao Li, Seung-Chul Lee, Pingfen Lin, Yun Chiu:
A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion. IEEE Trans. Circuits Syst. II Express Briefs 57-II(11): 853-857 (2010) - [j5]Bei Peng, Hao Li, Pingfen Lin, Yun Chiu:
An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 961-965 (2010) - [c9]Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4 - [c8]Peiyuan Wan, Yun Chiu, Pingfen Lin:
A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3. CICC 2010: 1-4 - [c7]Wenbo Liu, Pingli Huang, Yun Chiu:
A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR. ISSCC 2010: 380-381
2000 – 2009
- 2009
- [j4]Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu:
A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation. IEEE J. Sel. Top. Signal Process. 3(3): 374-383 (2009) - [c6]Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu:
CMOS RF transmitter with integrated power amplifier utilizing digital equalization. CICC 2009: 403-406 - [c5]Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu:
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83 - 2008
- [j3]Richard Tseng, Ada S. Y. Poon, Yun Chiu:
A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 479-483 (2008) - [c4]Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic:
Background ADC calibration in digital domain. CICC 2008: 301-304 - [c3]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. ESSCIRC 2008: 90-93 - 2007
- [c2]Pingli Huang, Yun Chiu:
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs. ISCAS 2007: 1241-1244 - 2005
- [c1]Yun Chiu, Borivoje Nikolic, Paul R. Gray:
Scaling of analog-to-digital converters into ultra-deep-submicron CMOS. CICC 2005: 375-382 - 2004
- [j2]Yun Chiu, Paul R. Gray, Borivoje Nikolic:
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE J. Solid State Circuits 39(12): 2139-2151 (2004) - [j1]Yun Chiu, Cheongyuen W. Tsang, Borivoje Nikolic, Paul R. Gray:
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 38-46 (2004)
Coauthor Index
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