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2020 – today
- 2024
[j104]Yanggon Kim
, Yunki Han, Jaekang Shin, Junkyum Kim, Lee-Sup Kim:
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications. IEEE Comput. Archit. Lett. 23(1): 41-44 (2024)- [j103]Hyeonuk Kim, Youngbeom Jung, Lee-Sup Kim:
ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks. IEEE Trans. Computers 73(2): 353-365 (2024) - [j102]Myeonggu Kang, Junyoung Park, Hyein Shin, Jaekang Shin, Lee-Sup Kim:
ToEx: Accelerating Generation Stage of Transformer-Based Language Models via Token-Adaptive Early Exit. IEEE Trans. Computers 73(9): 2248-2261 (2024) - [i1]Junyoung Park, Myeonggu Kang, Yunki Han, Yanggon Kim, Jaekang Shin, Lee-Sup Kim:
Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation. CoRR abs/2407.15131 (2024) - 2023
- [j101]Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators. IEEE Trans. Computers 72(7): 2011-2024 (2023) - [j100]Myeonggu Kang, Hyein Shin, Junkyum Kim, Lee-Sup Kim:
MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT. IEEE Trans. Computers 72(11): 3140-3152 (2023) - [j99]Youngbeom Jung, Hyeonuk Kim, Seungkyu Choi, Jaekang Shin, Lee-Sup Kim:
Energy-Efficient CNN Personalized Training by Adaptive Data Reformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 332-336 (2023) - [j98]Seungkyu Choi, Jaekang Shin, Lee-Sup Kim:
Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1574-1587 (2023) - [c95]Junkyum Kim, Myeonggu Kang, Yunki Han, Yanggon Kim, Lee-Sup Kim:
OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing. HPCA 2023: 611-623 - 2022
- [j97]Kangkyu Park, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim:
Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks. IEEE Trans. Computers 71(4): 795-808 (2022) - [j96]Seungkyu Choi, Jaekang Shin, Lee-Sup Kim:
A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type. IEEE Trans. Computers 71(5): 1216-1229 (2022) - [j95]Myeonggu Kang, Hyeonuk Kim, Hyein Shin, Jaehyeong Sim, Kyeonghan Kim, Lee-Sup Kim:
S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity. IEEE Trans. Computers 71(6): 1291-1304 (2022) - [j94]Yunki Han, Kangkyu Park, Youngbeom Jung, Lee-Sup Kim:
EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access. IEEE Trans. Computers 71(12): 3127-3139 (2022) - [j93]Myeonggu Kang, Hyein Shin, Lee-Sup Kim:
A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3026-3039 (2022) - [j92]Youngbeom Jung, Hyeonuk Kim, Yeongjae Choi, Lee-Sup Kim:
Quantization-Error-Robust Deep Neural Network for Embedded Accelerators. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 609-613 (2022) - [c94]Jaekang Shin, Seungkyu Choi, Jongwoo Ra, Lee-Sup Kim:
Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN. DAC 2022: 253-258 - [c93]Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators. ICCAD 2022: 40:1-40:9 - 2021
- [j91]Hoseok Seol, Minhye Kim, Taesoo Kim, Yongdae Kim, Lee-Sup Kim:
Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks. IEEE Trans. Computers 70(4): 539-551 (2021) - [c92]Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices. DAC 2021: 1039-1044 - [c91]HanCheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator. DAC 2021: 1087-1092 - [c90]Seungkyu Choi, Jaekang Shin, Lee-Sup Kim:
A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation. ICCAD 2021: 1-9 - [c89]Myeonggu Kang, Hyein Shin, Jaekang Shin, Lee-Sup Kim:
A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators. ICCAD 2021: 1-9 - [c88]Kangkyu Park, Yunki Han, Lee-Sup Kim:
Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity. ICCAD 2021: 1-9 - 2020
- [j90]Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim:
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices. IEEE J. Solid State Circuits 55(10): 2691-2702 (2020) - [j89]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyun-Kyu Jeon, Byung-Guk Kim, Lee-Sup Kim:
A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 67-71 (2020) - [j88]Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim:
CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. 67-II(12): 3337-3341 (2020) - [j87]Jaehyeong Sim, Somin Lee, Lee-Sup Kim:
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 87-100 (2020) - [c87]Jaekang Shin, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim:
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates. DAC 2020: 1-6 - [c86]Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration. ICCAD 2020: 102:1-102:9
2010 – 2019
- 2019
- [j86]Jaemin Jang, Wongyu Shin, Jungwhan Choi, Yongju Kim, Lee-Sup Kim:
Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory. IEEE Trans. Computers 68(5): 752-764 (2019) - [j85]Jungwhan Choi, Jaemin Jang, Lee-Sup Kim:
DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells. IEEE Trans. Computers 68(12): 1741-1754 (2019) - [j84]Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim:
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1972-1976 (2019) - [j83]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 724-728 (2019) - [c85]Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim:
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices. A-SSCC 2019: 57-60 - [c84]Seungkyu Choi, Jaekang Shin, Yeongjae Choi, Lee-Sup Kim:
An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices. DAC 2019: 191 - [c83]Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim:
NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks. HPCA 2019: 661-673 - [c82]Youngbeom Jung, Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim:
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators. ICCAD 2019: 1-8 - [c81]Kyeonghan Kim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim:
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM. ICCAD 2019: 1-8 - [c80]Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim:
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks. ICCAD 2019: 1-8 - [c79]Hyeonwook Wi, Hyeonuk Kim, Seungkyu Choi, Lee-Sup Kim:
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration. ISLPED 2019: 1-6 - [c78]Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. VLSI Circuits 2019: 196- - 2018
- [j82]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim:
Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs. IEEE Trans. Computers 67(10): 1403-1415 (2018) - [j81]Yong-Hun Kim, Dongil Lee, Daewoong Lee, Lee-Sup Kim:
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1539-1543 (2018) - [j80]Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim:
A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1564-1568 (2018) - [c77]Jaehyeong Sim, Hoseok Seol, Lee-Sup Kim:
NID: processing binary convolutional neural network in commodity DRAM. ICCAD 2018: 10 - [c76]Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim:
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training. ISLPED 2018: 19:1-19:6 - 2017
- [j79]Jaemin Jang, Wongyu Shin, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Yongju Kim, Lee-Sup Kim:
Refresh-Aware Write Recovery Memory Controller. IEEE Trans. Computers 66(4): 688-701 (2017) - [j78]Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim:
Rank-Level Parallelism in DRAM. IEEE Trans. Computers 66(7): 1274-1280 (2017) - [j77]Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
Bank-Group Level Parallelism. IEEE Trans. Computers 66(8): 1428-1434 (2017) - [j76]Yong-Hun Kim, Taeho Lee, Hyun-Kyu Jeon, Dongil Lee, Lee-Sup Kim:
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 823-835 (2017) - [j75]Yeongjae Choi, Dongmyung Bae, Jaehyeong Sim, Seungkyu Choi, Minhye Kim, Lee-Sup Kim:
Energy-Efficient Design of Processing Element for Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1332-1336 (2017) - [j74]Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 380-384 (2017) - [j73]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
In-DRAM Data Initialization. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3251-3254 (2017) - [c75]Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim:
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks. DAC 2017: 60:1-60:6 - [c74]Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, Lee-Sup Kim:
SENIN: An energy-efficient sparse neuromorphic system with on-chip learning. ISLPED 2017: 1-6 - [c73]Yeongjae Choi, Jun-Seok Park, Lee-Sup Kim:
Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph Cut in Resistor Grid. WACV 2017: 778-786 - 2016
- [j72]Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim:
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation. IEEE Trans. Computers 65(7): 2213-2227 (2016) - [j71]Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Youngsuk Moon, Yongkee Kwon, Lee-Sup Kim:
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing. IEEE Trans. Computers 65(10): 3027-3040 (2016) - [j70]Sang-Hye Chung, Young-Ju Kim, Yong-Hun Kim, Lee-Sup Kim:
A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 264-268 (2016) - [j69]Dongil Lee, Taeho Lee, Young-Ju Kim, Lee-Sup Kim:
A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 733-737 (2016) - [j68]Jun-Seok Park, Hyo-Eun Kim, Hong-Yun Kim, Jaeyoung Lee, Lee-Sup Kim:
A Vision Processor With a Unified Interest-Point Detection and Matching Hardware for Accelerating a Stereo-Matching Algorithm. IEEE Trans. Circuits Syst. Video Technol. 26(12): 2328-2343 (2016) - [j67]Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim:
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 789-793 (2016) - [j66]Taeho Lee, Yong-Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim:
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1450-1459 (2016) - [c72]Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim:
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity. ISCA 2016: 719-730 - [c71]Minhye Kim, Soochang Chae, Young-Ju Kim, Seung-Jun Bae, Lee-Sup Kim:
Crosstalk avoidance code for direct pass-through architecture. ISCAS 2016: 2475-2478 - [c70]Jaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae, Yeongjae Choi, Lee-Sup Kim:
14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems. ISSCC 2016: 264-265 - 2015
- [j65]Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim:
Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing. IEEE J. Solid State Circuits 50(2): 610-618 (2015) - [j64]Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim:
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2495-2503 (2015) - [j63]Yong-Hun Kim, Young-Ju Kim, Tae-Ho Lee, Lee-Sup Kim:
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 588-592 (2015) - [j62]Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 988-992 (2015) - [j61]Sang-Hye Chung, Lee-Sup Kim:
A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2023-2033 (2015) - [c69]Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim:
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. CICC 2015: 1-4 - [c68]Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim:
Multiple clone row DRAM: a low latency and area optimized DRAM. ISCA 2015: 223-234 - [c67]Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim:
An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. ISCAS 2015: 1830-1833 - 2014
- [j60]Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim:
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 61-II(3): 153-157 (2014) - [j59]Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2482-2490 (2014) - [j58]Kyu-Dong Hwang, Lee-Sup Kim:
A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 3016-3024 (2014) - [c66]Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-Sup Kim:
NUAT: A non-uniform access time memory controller. HPCA 2014: 464-475 - [c65]Jaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim:
Timing error masking by exploiting operand value locality in SIMD architecture. ICCD 2014: 90-96 - [c64]Wongyu Shin, Seungwook Paek, Lee-Sup Kim:
An area-efficient on-chip temperature sensor with nonlinearity compensation using injection-locked oscillator (ILO). ISCAS 2014: 1845-1848 - 2013
- [j57]Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim:
A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing. IEEE J. Solid State Circuits 48(8): 1970-1985 (2013) - [j56]Seungwook Paek, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim:
PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1509-1519 (2013) - [j55]Won-Young Lee, Jiehwan Oh, Lee-Sup Kim:
A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD. IEEE Trans. Circuits Syst. II Express Briefs 60-II(1): 21-25 (2013) - [j54]Hong-Yun Kim, Young-Jun Kim, Jiehwan Oh, Lee-Sup Kim:
A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 938-950 (2013) - [j53]Kyu-Dong Hwang, Lee-Sup Kim:
A 6.5-Gb/s 1-mW/Gb/s/CH Simple Capacitive Crosstalk Compensator in a 130-nm Process. IEEE Trans. Circuits Syst. II Express Briefs 60-II(6): 302-306 (2013) - [j52]Jun-Seok Park, Hyo-Eun Kim, Lee-Sup Kim:
A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-µm CMOS Technology. IEEE Trans. Circuits Syst. Video Technol. 23(5): 832-845 (2013) - [j51]Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 206-216 (2013) - [c63]Jeongmin Yang, Young-Ju Kim, Lee-Sup Kim:
A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator. ISCAS 2013: 1392-1395 - [c62]Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim:
All-digital hybrid temperature sensor network for dense thermal monitoring. ISSCC 2013: 260-261 - [c61]Ji-Hwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo-Sun Choi, Lee-Sup Kim:
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. ISSCC 2013: 410-411 - 2012
- [j50]Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim:
MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization. IEEE J. Solid State Circuits 47(2): 518-535 (2012) - [j49]Won-Young Lee, Lee-Sup Kim:
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2518-2528 (2012) - [j48]Won-Young Lee, Kyu-Dong Hwang, Lee-Sup Kim:
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2858-2866 (2012) - [j47]Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim:
A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer. IEEE Trans. Circuits Syst. Video Technol. 22(4): 589-604 (2012) - [j46]Won-Young Lee, Lee-Sup Kim:
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 964-968 (2012) - [j45]Seok-Hoon Kim, Sung-Eui Yoon, Sang-Hye Chung, Young-Jun Kim, Hong-Yun Kim, Kyusik Chung, Lee-Sup Kim:
A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1082-1093 (2012) - [j44]Young-Jun Kim, Hyo-Eun Kim, Seok-Hoon Kim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim:
Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1691-1704 (2012) - [c60]Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim:
A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing. CICC 2012: 1-4 - [c59]Seungwook Paek, Seok-Hwan Moon, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim:
PowerField: a transient temperature-to-power technique based on Markov random field theory. DAC 2012: 630-635 - [c58]Yong-Hun Kim, Lee-Sup Kim:
A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient. ISCAS 2012: 321-324 - [c57]Sang-Hye Chung, Lee-Sup Kim:
1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. VLSIC 2012: 144-145 - 2011
- [j43]Won-Young Lee, Lee-Sup Kim:
A Spread Spectrum Clock Generator for DisplayPort Main Link. IEEE Trans. Circuits Syst. II Express Briefs 58-II(6): 361-365 (2011) - [j42]Mi-Jo Kim, Lee-Sup Kim:
A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 477-481 (2011) - [j41]Hong-Yun Kim, Chang-Hyo Yu, Lee-Sup Kim:
A Memory-Efficient Unified Early Z-Test. IEEE Trans. Vis. Comput. Graph. 17(9): 1286-1294 (2011) - [j40]Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 525-537 (2011) - [c56]Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim:
A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS. CICC 2011: 1-4 - [c55]Won-Young Lee, Lee-Sup Kim:
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. ISCAS 2011: 430-433 - [c54]Seungwook Paek, Jiehwan Oh, Sang-Hye Chung, Lee-Sup Kim:
Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors. ISCAS 2011: 1664-1667 - [c53]Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim:
A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. ISSCC 2011: 128-130 - 2010
- [j39]Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim:
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. IEEE J. Solid State Circuits 45(2): 497 (2010) - [j38]Seok-Hoon Kim, Hong-Yun Kim, Young-Jun Kim, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. IEEE J. Solid State Circuits 45(3): 652-667 (2010) - [j37]Hye-Yoon Joo, Lee-Sup Kim:
A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 228-232 (2010) - [c52]Mi-Jo Kim, Lee-Sup Kim:
100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. CICC 2010: 1-4 - [c51]Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim:
Reconfigurable mobile stream processor for ray tracing. CICC 2010: 1-4 - [c50]Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim:
A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. ISCAS 2010: 1300-1303 - [c49]Kyu-Dong Hwang, Lee-Sup Kim:
An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages. ISCAS 2010: 3973-3976 - [c48]Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality. ISSCC 2010: 336-337
2000 – 2009
- 2009
- [j36]Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. Comput. Graph. 33(5): 625-637 (2009) - [j35]Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. IEEE J. Solid State Circuits 44(5): 1522-1530 (2009) - [j34]Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim:
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme. IEEE J. Solid State Circuits 44(8): 2222-2232 (2009) - [j33]Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. IEEE J. Solid State Circuits 44(11): 3146-3162 (2009) - [j32]Donghyun Kim, Lee-Sup Kim:
A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency. IEEE Trans. Computers 58(7): 890-901 (2009) - [j31]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, Lee-Sup Kim:
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1369-1382 (2009) - [c47]Won-Young Lee, Lee-Sup Kim:
A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link. ISCAS 2009: 185-188 - [c46]Young-Jun Kim, Kyusik Chung, Lee-Sup Kim, Seong Mo Park:
Bank-partition and Multi-fetch Scheme for Floating-point Special Function units in Multi-core Systems. ISCAS 2009: 1803-1806 - [c45]Kyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim:
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. ISSCC 2009: 138-139 - 2008
- [j30]Donghyun Kim, Lee-Sup Kim:
Area-efficient pixel rasterization and texture coordinate interpolation. Comput. Graph. 32(6): 669-681 (2008) - [j29]Jong-Sun Kim, Lee-Sup Kim:
Noise Robust Motion Refinement for Motion Compensated Noise Reduction. IEICE Trans. Inf. Syst. 91-D(5): 1581-1583 (2008) - [j28]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 43(2): 541-549 (2008) - [j27]Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, Yun-Gu Lee, HyunWook Park, Jong Beom Ra, Lee-Sup Kim:
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine. IEEE J. Solid State Circuits 43(5): 1247-1259 (2008) - [j26]Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1929-1938 (2008) - [c44]Kyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine. CICC 2008: 367-370 - [c43]Jae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu, Lee-Sup Kim:
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache. CICC 2008: 539-542 - [c42]Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim:
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme. CICC 2008: 639-642 - [c41]Hyun-Kyu Jeon, Hye-Ran Kim, Jung-Min Choi, Ju-Pyo Hong, Yong-Suk Kim, Hyung-Seog Oh, Dae-Keun Han, Lee-Sup Kim:
High speed serial interface for mobile LCD driver IC. ISCAS 2008: 157-160 - [c40]Jeong-Hyun Kim, Kyusik Chung, Young-Jun Kim, Seok-Hoon Kim, Lee-Sup Kim:
Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm. ISCAS 2008: 3534-3537 - 2007
- [j25]Jong-Sun Kim, Lee-Sup Kim:
Binary Motion Estimation with Hybrid Distortion Measure. IEICE Trans. Inf. Syst. 90-D(9): 1474-1477 (2007) - [j24]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches. IEEE J. Solid State Circuits 42(10): 2257-2269 (2007) - [c39]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems. CICC 2007: 579-582 - [c38]Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. ISCAS 2007: 765-768 - [c37]Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, HyunWook Park, Lee-Sup Kim:
A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. ISSCC 2007: 276-602 - [c36]Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL with Jitter-Reduction Techniques for DRAM Interfaces. ISSCC 2007: 496-497 - 2006
- [j23]Donghyun Kim, Kyusik Chung, Chang-Hyo Yu, Chun-Ho Kim, Inho Lee, Jaewan Bae, Young-Jun Kim, Jae-Hyeon Park, Sungbeen Kim, Yong-Ha Park, Nak Hee Seong, Jin-Aeon Lee, Jaehong Park, Stephen Oh, Seh-Woong Jeong, Lee-Sup Kim:
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications. IEEE J. Solid State Circuits 41(1): 71-84 (2006) - [j22]Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 254-267 (2006) - [j21]Byung-Do Yang, Lee-Sup Kim:
A low-power ROM using single charge-sharing capacitor and hierarchical bit line. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 313-322 (2006) - [c35]Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim:
An efficient texture cache for programmable vertex shaders. ISCAS 2006 - [c34]Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim:
Vertex cache of programmable geometry processor for mobile multimedia application. ISCAS 2006 - [c33]Kyung-Soo Ha, Lee-Sup Kim:
Charge-pump reducing current mismatch in DLLs and PLLs. ISCAS 2006 - [c32]Ju-Pyo Hong, Kyung-Soo Ha, Lee-Sup Kim:
A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver. ISCAS 2006 - [c31]Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim:
A low power SoC bus with low-leakage and low-swing technique. ISCAS 2006 - [c30]Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. ISSCC 2006: 1606-1615 - [c29]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. ISSCC 2006: 2152-2159 - 2005
- [j20]Chang-Young Han, Yeon-Ho Im, Lee-Sup Kim:
Geometry engine architecture with early backface culling hardware. Comput. Graph. 29(3): 415-425 (2005) - [j19]Joung-Youn Kim, Lee-Sup Kim:
An Efficient Memory Address Converter for Soc-based 3d Graphics System. J. Circuits Syst. Comput. 14(4): 861-876 (2005) - [j18]Byung-Guk Kim, Lee-Sup Kim:
A 250-MHz-2-GHz wide-range delay-locked loop. IEEE J. Solid State Circuits 40(6): 1310-1321 (2005) - [j17]Byung-Do Yang, Lee-Sup Kim:
A low-power SRAM using hierarchical bit line and local sense amplifiers. IEEE J. Solid State Circuits 40(6): 1366-1376 (2005) - [j16]Byung-Do Yang, Lee-Sup Kim:
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. IEEE J. Solid State Circuits 40(8): 1736-1744 (2005) - [j15]Yeon-Ho Im, Chang-Young Han, Lee-Sup Kim:
A Method to Generate Soft Shadows Using a Layered Depth Image and Warping. IEEE Trans. Vis. Comput. Graph. 11(3): 265-272 (2005) - [c28]Byung-Guk Kim, Kwang-Il Oh, Lee-Sup Kim, Dae-Woo Lee:
A 500MHz DLL with second order duty cycle corrector for low jitter. CICC 2005: 325-328 - [c27]Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. ISCAS (5) 2005: 4546-4549 - [c26]Jaewan Bae, Donghyun Kim, Lee-Sup Kim:
An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. ISCAS (5) 2005: 4570-4573 - [c25]Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim:
A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. ISCAS (5) 2005: 4574-4577 - 2004
- [j14]Donghyun Kim, Lee-Sup Kim:
An Efficient Fragment Processing Technique in A-Buffer Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 87-A(1): 258-269 (2004) - [j13]Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu:
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. IEEE J. Solid State Circuits 39(5): 761-774 (2004) - [j12]Kihyuk Sung, Lee-Sup Kim:
A high-resolution synchronous mirror delay using successive approximation register. IEEE J. Solid State Circuits 39(11): 1997-2004 (2004) - [c24]Byung-Guk Kim, Lee-Sup Kim:
A 250MHz-2GHz wide range delay-locked loop. CICC 2004: 139-142 - [c23]Chun-Ho Kim, Lee-Sup Kim:
Adaptive Selection of an Index in a Texture Cache. ICCD 2004: 295-300 - [c22]Chang-Hyo Yu, Lee-Sup Kim:
An adaptive spatial filter for early depth test. ISCAS (2) 2004: 137-140 - [c21]Donghyun Kim, Lee-Sup Kim:
Division-free rasterizer for perspective-correct texture filtering. ISCAS (2) 2004: 153-156 - [c20]Byung-Do Yang, Lee-Sup Kim:
An error pattern ROM compression method for continuous data. ISCAS (2) 2004: 845-848 - [c19]Kwang-Il Oh, Lee-Sup Kim:
A high performance low power dynamic PLA with conditional evaluation scheme. ISCAS (2) 2004: 881-884 - 2003
- [j11]Byung-Do Yang, Lee-Sup Kim:
A low-power ROM using charge recycling and charge sharing techniques. IEEE J. Solid State Circuits 38(4): 641-653 (2003) - [j10]Chun-Ho Kim, Si-Mun Seong, Jin-Aeon Lee, Lee-Sup Kim:
Winscale: an image-scaling algorithm using an area pixel model. IEEE Trans. Circuits Syst. Video Technol. 13(6): 549-553 (2003) - [j9]Byung-Do Yang, Lee-Sup Kim:
A low-power charge-recycling ROM architecture. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 590-600 (2003) - [c18]Byung-Do Yang, Lee-Sup Kim:
A low power charge sharing ROM using dummy bit lines. ISCAS (5) 2003: 377-380 - [c17]Inho Lee, Joung-Youn Kim, Yeon-Ho Im, Yunseok Choi, Hyunchul Shin, Chang-Young Han, Donghyun Kim, Hyoungjoon Park, Young-Il Seo, Kyusik Chung, Chang-Hyo Yu, Kanghyup Chun, Lee-Sup Kim:
A hardware-like high-level language based environment for 3D graphics architecture exploration. ISCAS (2) 2003: 512-515 - [c16]Chang-Hyo Yu, Lee-Sup Kim:
A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter. ISCAS (2) 2003: 724-727 - [c15]Kyusik Chung, Lee-Sup Kim:
A PN triangle generation unit for fast and simple tessellation hardware. ISCAS (2) 2003: 728-731 - [c14]Kwang-Il Oh, Lee-Sup Kim:
A clock delayed sleep mode domino logic for wide dynamic OR gate. ISLPED 2003: 176-179 - 2002
- [c13]Byung-Do Yang, Lee-Sup Kim:
A ROM compression method for continuous data. CICC 2002: 119-122 - [c12]Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu:
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. ISCAS (5) 2002: 373-376 - [c11]Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim:
A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. ISCAS (1) 2002: 461-464 - 2001
- [j8]Joung-Youn Kim, Lee-Sup Kim, Seung-Ho Hwang:
An advanced contrast enhancement using partially overlapped sub-block histogram equalization. IEEE Trans. Circuits Syst. Video Technol. 11(4): 475-484 (2001) - [j7]Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A hardware cost minimized fast Phong shader. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 297-304 (2001) - [c10]Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
SPAF: Sub-texel Precision Anisotropic Filtering. Workshop on Graphics Hardware 2001: 99-107 - [c9]Hyeon-Cheol Mo, Jong-Sun Kim, Lee-Sup Kim:
A high-speed pattern decoder in MPEG-4 padding block hardware accelerator. ISCAS (2) 2001: 197-200 - [c8]Youngjoon Kim, Lee-Sup Kim:
A low power carry select adder with reduced area. ISCAS (4) 2001: 218-221 - [c7]Sunho Chang, Lee-Sup Kim:
Design trade-off in merged DRAM logic for video signal processing. ISCAS (5) 2001: 267-270 - [c6]Byung-Do Yang, Lee-Sup Kim:
A low power charge-recycling ROM architecture. ISCAS (4) 2001: 510-513 - 2000
- [j6]Jin-Aeon Lee, Lee-Sup Kim:
SPARP: a single pass antialiased rasterization processor. Comput. Graph. 24(2): 233-243 (2000) - [j5]Ki-Hyuk Sung, Lee-Sup Kim:
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". IEEE J. Solid State Circuits 35(6): 919-920 (2000) - [j4]Seung-Kwon Paek, Lee-Sup Kim:
A real-time wavelet vector quantization algorithm and its VLSI architecture. IEEE Trans. Circuits Syst. Video Technol. 10(3): 475-489 (2000) - [j3]Sunho Chang, Bum-Sik Kim, Lee-Sup Kim:
A programmable 3.2-GOPS merged DRAM logic for video signal processing. IEEE Trans. Circuits Syst. Video Technol. 10(6): 967-973 (2000) - [c5]Sunho Chang, Jong-Sun Kim, Lee-Sup Kim:
A Memory Architecture with 4-Address Configurations for Video Signal Processing. DATE 2000: 746 - [c4]Jin-Aeon Lee, Lee-Sup Kim:
Single-Pass Full-Screen Hardware Accelerated Antialiasing. Workshop on Graphics Hardware 2000: 67-76 - [c3]Joung-Youn Kim, Lee-Sup Kim, Seung-Ho Hwang:
An advanced contrast enhancement using partially overlapped sub-block histogram equalization. ISCAS 2000: 537-540
1990 – 1999
- 1998
- [c2]Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim:
A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics. ICCD 1998: 286-291 - 1997
- [c1]Bum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim:
A new 4-2 adder and booth selector for low power MAC unit. ISLPED 1997: 100-103 - 1994
- [j2]Masataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai:
A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. IEEE J. Solid State Circuits 29(12): 1482-1490 (1994)
1980 – 1989
- 1989
- [j1]Lee-Sup Kim, Robert W. Dutton:
Modeling of the distributed gate RC effect in MOSFET's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1365-1367 (1989)
Coauthor Index
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