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ORCIDSaurabh Sinha 0001
Person information
- affiliation: ARM Inc., Austin, TX, USA
Other persons with the same name
- Saurabh Sinha — disambiguation page
- Saurabh Sinha 0002
![[0000-0001-6033-7746]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0001-6033-7746")
— University of Illinois at Urbana-Champaign, IL, USA - Saurabh Sinha 0003 — IBM Research, Yorktown Heights, NY, USA (and 1 more)
- Saurabh Sinha 0004 — University of Canterbury, Christchurch, Canterbury, New Zealand
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2020 – today
- 2022
[j13]Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 410-423 (2022)- 2021
- [j12]Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz, Sung Kyu Lim:
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1152-1163 (2021) - [c50]Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni:
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC 2021: 1-2 - [i4]Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong:
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR abs/2109.07915 (2021) - 2020
- [c49]Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim:
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. ISPD 2020: 39-46 - [i3]Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric:
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR abs/2005.10866 (2020) - [i2]Rahul Mathur, Chien-Ju Chao, Rossana Liu, Nikhil Tadepalli, Pranavi Chandupatla, Shawn Hung, Xiaoqing Xu, Saurabh Sinha, Jaydeep Kulkarni:
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology. CoRR abs/2007.16179 (2020)
2010 – 2019
- 2019
- [j11]Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 888-898 (2019) - [c48]Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline:
Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. ISLPED 2019: 1-6 - 2018
- [c47]Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi:
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. DAC 2018: 28:1-28:6 - [i1]Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric:
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. CoRR abs/1807.11396 (2018) - 2017
- [j10]Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha:
Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Des. Test 34(2): 31-38 (2017) - [j9]Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2118-2129 (2017) - [c46]Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric:
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). ICCAD 2017: 999-1004 - [c45]Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim:
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). ICCAD 2017: 1005-1010 - [c44]Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED 2017: 1-6 - 2016
- [j8]Satish Chandra, Suresh Thummalapenta, Saurabh Sinha:
Lessons from the tech transfer trenches. Commun. ACM 59(2): 37-39 (2016) - [j7]Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric:
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. 10(6): 315-322 (2016) - [j6]Lawrence T. Clark, Vinay Vashishtha, Lucian Shifren, Aditya Gujja, Saurabh Sinha, Brian Cline, Chandarasekaran Ramamurthy, Greg Yeric:
ASAP7: A 7-nm finFET predictive process design kit. Microelectron. J. 53: 105-115 (2016) - [c43]Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. DAC 2016: 76:1-76:6 - [c42]Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Match-making for monolithic 3D IC: finding the right technology node. DAC 2016: 77:1-77:6 - [c41]Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim:
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD 2016: 130 - [c40]Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED 2016: 70-75 - [c39]Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED 2016: 41-48 - 2015
- [c38]Rahulkrishna Yandrapally, Giriprasad Sridhara, Saurabh Sinha:
Automated Modularization of GUI Test Cases. ICSE (1) 2015: 44-54 - [c37]Simon Holm Jensen, Suresh Thummalapenta, Saurabh Sinha, Satish Chandra:
Test Generation from Business Rules. ICST 2015: 1-10 - [c36]Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED 2015: 201-206 - [c35]Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov:
Circuit design perspectives for Ge FinFET at 10nm and beyond. ISQED 2015: 57-60 - 2014
- [j5]Hina Shah, Mary Jean Harrold, Saurabh Sinha:
Global software testing under deadline pressure: Vendor-side experiences. Inf. Softw. Technol. 56(1): 6-19 (2014) - [c34]Satish Chandra, Vibha Singhal Sinha, Saurabh Sinha, Krishna Ratakonda:
Software services: a research roadmap. FOSE 2014: 40-54 - [c33]Vibha Singhal Sinha, Pankaj Dhoolia, Senthil Mani, Saurabh Sinha:
Operational abstractions of model transforms. ISEC 2014: 3:1-3:10 - [c32]Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra:
Physical design and FinFETs. ISPD 2014: 65-68 - [c31]Rahulkrishna Yandrapally, Suresh Thummalapenta, Saurabh Sinha, Satish Chandra:
Robust test automation using contextual clues. ISSTA 2014: 304-314 - 2013
- [c30]Greg Yeric, Brian Cline, Saurabh Sinha, David Pietromonaco, Vikas Chandra, Rob Aitken:
The past present and future of design-technology co-optimization. CICC 2013: 1-8 - [c29]Suresh Thummalapenta, K. Vasanta Lakshmi, Saurabh Sinha, Nishant Sinha, Satish Chandra:
Guided test generation for web applications. ICSE 2013: 162-171 - [c28]Suresh Thummalapenta, Pranavadatta Devaki, Saurabh Sinha, Satish Chandra, Sivagami Gnanasundaram, Deepa D. Nagaraj, Sampathkumar Sathishkumar:
Efficient and change-resilient test automation: an industrial case study. ICSE 2013: 1002-1011 - 2012
- [c27]Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao:
Exploring sub-20nm FinFET design with predictive technology models. DAC 2012: 283-288 - [c26]Suresh Thummalapenta, Saurabh Sinha, Nimit Singhania, Satish Chandra:
Automating test automation. ICSE 2012: 881-891 - [c25]Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao:
Design benchmarking to 7nm with FinFET predictive technology models. ISLPED 2012: 15-20 - [c24]Suresh Thummalapenta, Nimit Singhania, Pranavadatta Devaki, Saurabh Sinha, Satish Chandra, Achin K. Das, Srinivas Mangipudi:
Efficiently scripting change-resilient tests. SIGSOFT FSE 2012: 41 - 2011
- [j4]Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao:
Workload-Aware Neuromorphic Design of the Power Controller. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 381-390 (2011) - [c23]Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao:
A workload-aware neuromorphic controller for dynamic power and thermal management. AHS 2011: 200-207 - [c22]Monika Gupta, Debdoot Mukherjee, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha:
Serving Information Needs in Business Process Consulting. BPM 2011: 231-247 - [c21]Hina Shah, Saurabh Sinha, Mary Jean Harrold:
Outsourced, Offshored Software-Testing Practice: Vendor-Side Experiences. ICGSE 2011: 131-140 - [c20]Vibha Singhal Sinha, Senthil Mani, Saurabh Sinha:
Entering the circle of trust: developer initiation as committers in open-source projects. MSR 2011: 133-142 - 2010
- [c19]Debdoot Mukherjee, Pankaj Dhoolia, Saurabh Sinha, Aubrey J. Rembert, Mangala Gowri Nanda:
From Informal Process Diagrams to Formal Process Models. BPM 2010: 145-161 - [c18]Pankaj Dhoolia, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha:
Debugging Model-Transformation Failures Using Dynamic Tainting. ECOOP 2010: 26-51 - [c17]Mangala Gowri Nanda, Monika Gupta, Saurabh Sinha, Satish Chandra, David Schmidt, Pradeep Balachandran:
Making defect-finding tools work for you. ICSE (2) 2010: 99-108 - [c16]Mijung Kim, Saurabh Sinha, Carsten Görg, Hina Shah, Mary Jean Harrold, Mangala Gowri Nanda:
Automated Bug Neighborhood Analysis for Identifying Incomplete Bug Fixes. ICST 2010: 383-392 - [c15]Vibha Singhal Sinha, Saurabh Sinha, Swathi Rao:
BUGINNINGS: identifying the origins of a bug. ISEC 2010: 3-12 - [c14]Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao:
Workload-aware neuromorphic design of low-power supply voltage controller. ISLPED 2010: 241-246 - [c13]Senthil Mani, Vibha Singhal Sinha, Pankaj Dhoolia, Saurabh Sinha:
Automated support for repairing input-model faults. ASE 2010: 195-204
2000 – 2009
- 2009
- [j3]Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao:
The Predictive Technology Model in the Late Silicon Era and Beyond. Found. Trends Electron. Des. Autom. 3(4): 305-401 (2009) - [c12]Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao:
Enabling resonant clock distribution with scaled on-chip magnetic inductors. ICCD 2009: 103-108 - [c11]Mangala Gowri Nanda, Saurabh Sinha:
Accurate Interprocedural Null-Dereference Analysis for Java. ICSE 2009: 133-143 - [c10]Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha, Pankaj Dhoolia, Debdoot Mukherjee, Soham Chakraborty:
Efficient Testing of Service-Oriented Applications Using Semantic Service Stubs. ICWS 2009: 197-204 - [c9]Saurabh Sinha, Hina Shah, Carsten Görg, Shujuan Jiang, Mijung Kim, Mary Jean Harrold:
Fault localization and repair for Java runtime exceptions. ISSTA 2009: 153-164 - [c8]Mangala Gowri Nanda, Senthil Mani, Vibha Singhal Sinha, Saurabh Sinha:
Demystifying model transformations: an approach based on automated rule inference. OOPSLA 2009: 341-360 - 2008
- [c7]Saurabh Sinha, Asha Balijepalli, Yu Cao:
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. ISQED 2008: 502-507 - 2007
- [c6]Asha Balijepalli, Saurabh Sinha, Yu Cao:
Compact modeling of carbon nanotube transistor for early stage process-design exploration. ISLPED 2007: 2-7 - 2006
- [c5]Raúl A. Santelices, Saurabh Sinha, Mary Jean Harrold:
Subsumption of program entities for efficient coverage and monitoring. SOQUA 2006: 2-5 - 2001
- [j2]Saurabh Sinha, Mary Jean Harrold, Gregg Rothermel:
Interprocedural control dependence. ACM Trans. Softw. Eng. Methodol. 10(2): 209-254 (2001) - 2000
- [j1]Saurabh Sinha, Mary Jean Harrold:
Analysis and Testing of Programs with Exception Handling Constructs. IEEE Trans. Software Eng. 26(9): 849-871 (2000)
1990 – 1999
- 1999
- [c4]Saurabh Sinha, Mary Jean Harrold, Gregg Rothermel:
System-Dependence-Graph-Based Slicing of Programs with Arbitrary Interprocedural Control Flow. ICSE 1999: 432-441 - [c3]Saurabh Sinha, Mary Jean Harrold:
Criteria for Testing Exception-Handling Constructs in Java Programs. ICSM 1999: 265- - 1998
- [c2]Saurabh Sinha, Mary Jean Harrold:
Analysis of Programs with Exception-Handling Constructs. ICSM 1998: 348-357 - [c1]Mary Jean Harrold, Gregg Rothermel, Saurabh Sinha:
Computation of Interprocedural Control Dependence. ISSTA 1998: 11-20
Coauthor Index
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