17th ISQED 2016: Santa Clara, California, USA

Session 1A: Low Power Memory & Logic Design

Session 1B: Advanced Three-Dimensional Integrated Circuits

Session 2A: Network on a Chip

Session 2C: Circuits and Architecture for Emerging Logic and Memory Technologies

Session 3A: On-Chip Machine Learning and Neuromorphic Computing

Session P: Poster Presentations

Session 4B: Enabling 5nm Technology Node

Session 4C: Advanced Testing Concepts

Session 5A: Embedded Systems

Session 5B: Hardware and System Security

Session 5C: Analog Design

Session 6A: Design Optimization for Performance, Reliability, and Yield

Session 6B: EDA for Design Exploration & Analysis Beyond Moore's Law

Session 6C: Sensors for lOT

a service of Schloss Dagstuhl - Leibniz Center for Informatics