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ORCIDAndrew A. Kennings
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- affiliation: University of Waterloo, Department of Electrical and Computer Engineering
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Journal Articles
- 2020
[j12]Aysa Fakheri Tabrizi
, Nima Karimpour Darav, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat:
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1177-1190 (2020)- 2018
- [j11]Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, David T. Westwick, Laleh Behjat:
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints. ACM Trans. Design Autom. Electr. Syst. 23(4): 43:1-43:25 (2018) - 2016
- [j10]Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat:
Eh?Placer: A High-Performance Modern Technology-Driven Placer. ACM Trans. Design Autom. Electr. Syst. 21(3): 37:1-37:27 (2016) - 2012
- [j9]Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings:
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1305-1318 (2012) - 2011
- [j8]Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox:
FPGA technology mapping with encoded libraries and staged priority cuts. ACM Trans. Reconfigurable Technol. Syst. 4(4): 35:1-35:17 (2011) - 2010
- [j7]Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu:
Power minimisation during field programmable gate array placement. IET Comput. Digit. Tech. 4(3): 170-183 (2010) - 2009
- [j6]Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene:
Improving Simulated Annealing-Based FPGA Placement With Directed Moves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 179-192 (2009) - 2007
- [j5]Jianhua Li, Laleh Behjat, Andrew A. Kennings:
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 669-679 (2007) - 2006
- [j4]Andrew A. Kennings, Kristofer Vorwerk:
Force-Directed Methods for Generic Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2076-2087 (2006) - 2005
- [j3]Miguel F. Anjos, Andrew A. Kennings, Anthony Vannelli:
A semidefinite optimization approach for the single-row layout problem with unequal dimensions. Discret. Optim. 2(2): 113-122 (2005) - 2004
- [j2]William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola:
Segmented channel routability via satisfiability. ACM Trans. Design Autom. Electr. Syst. 9(4): 517-528 (2004) - 2003
- [j1]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola:
Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 511-514 (2003)
Conference and Workshop Papers
- 2019
- [c36]Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu:
Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer. FPGA 2019: 122-131 - 2018
- [c35]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat:
A machine learning framework to identify detailed routing short violations from a placed netlist. DAC 2018: 48:1-48:6 - 2017
- [c34]Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Ravi Mamidi:
ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks. ICCAD 2017: 867-871 - [c33]Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat:
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement. ISPD 2017: 141-148 - [c32]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew A. Kennings, Laleh Behjat:
Detailed routing violation prediction during placement using machine learning. VLSI-DAT 2017: 1-4 - 2016
- [c31]Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat:
Routing-Aware Incremental Timing-Driven Placement. ISVLSI 2016: 290-295 - 2015
- [c30]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). FPGA 2015: 266 - [c29]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
Voltage-Boosted Synchronizers. ACM Great Lakes Symposium on VLSI 2015: 307-312 - [c28]Nima Karimpour Darav, Andrew A. Kennings, David T. Westwick, Laleh Behjat:
High Performance Global Placement and Legalization Accounting for Fence Regions. ICCAD 2015: 514-519 - [c27]Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat:
A Detailed Routing-Aware Detailed Placement Technique. ISVLSI 2015: 38-43 - [c26]Nima Karimpour Darav, Amin Farshidi, Aysa Fakheri Tabrizi, Emily Marasco, Amir Karbalaei, Andrew A. Kennings, Ismail S. Bustany, Laleh Behjat:
The impact of industry-organized contests on EDA education. MSE 2015: 21-24 - [c25]Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
Runtime slack-deficit detection for a low-voltage DCT circuit. MWSCAS 2015: 1-4 - 2014
- [c24]Andrew A. Kennings, Nima Karimpour Darav, Laleh Behjat:
Detailed placement accounting for technology constraints. VLSI-SoC 2014: 1-6 - 2012
- [c23]Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings:
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). FPGA 2012: 266 - [c22]Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. FPL 2012: 41-48 - [c21]Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. ISQED 2012: 617-624 - [c20]Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson:
FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC 2012: 271-274 - 2011
- [c19]Andrew A. Kennings, Chirag Ravishankar:
Parallel FPGA technology mapping using multi-core architectures. CCECE 2011: 274-279 - 2010
- [c18]Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu:
Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL 2010: 532-537 - 2009
- [c17]Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox:
FPGA technology mapping with encoded libraries andstaged priority cuts. FPGA 2009: 143-150 - [c16]Val Pevzner, Andrew A. Kennings, Andy Fox:
Physical optimization for FPGAs using post-placement topology rewriting. ISPD 2009: 91-98 - 2008
- [c15]Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings:
A technique for minimizing power during FPGA placement. FPL 2008: 233-238 - 2007
- [c14]Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings:
Improving Timing-Driven FPGA Packing With Physical Information. FPL 2007: 117-123 - [c13]Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen:
Improving Annealing Via Directed Moves. FPL 2007: 363-370 - [c12]Alexander Wong, Andrew A. Kennings:
Adaptive multiple texture approach to texture packing for 3D video games. Future Play 2007: 189-196 - [c11]Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat:
Floorplan repair using dynamic whitespace management. ACM Great Lakes Symposium on VLSI 2007: 552-557 - 2005
- [c10]Austin Hung, William D. Bishop, Andrew A. Kennings:
Symmetric Multiprocessing on Programmable Chips Made Easy. DATE 2005: 240-245 - [c9]Kristofer Vorwerk, Andrew A. Kennings:
An Improved Multi-Level Framework for Force-Directed Placement. DATE 2005: 902-907 - [c8]Kristofer Vorwerk, Andrew A. Kennings:
Mixed-size placement via line search. ICCAD 2005: 899-904 - 2004
- [c7]Austin Hung, William D. Bishop, Andrew A. Kennings:
Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips. ERSA 2004: 312 - [c6]Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli:
Engineering details of a stable force-directed placer. ICCAD 2004: 573-580 - 2002
- [c5]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings:
Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI 2002: 130-135 - [c4]William N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings:
On segmented channel routability. ISCAS (1) 2002: 169-172 - 2000
- [c3]Andrew A. Kennings, Igor L. Markov:
Analytical minimization of half-perimeter wirelength. ASP-DAC 2000: 179-184 - 1999
- [c2]Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
Function Smoothing with Applications to VLSI Layout. ASP-DAC 1999: 225- - [c1]Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC 1999: 349-354
Editorship
- 2008
- [e2]Ion I. Mandoiu, Andrew A. Kennings:
The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings. ACM 2008, ISBN 978-1-59593-918-0 [contents] - 2007
- [e1]Andrew A. Kennings, Ion I. Mandoiu:
The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings. ACM 2007, ISBN 978-1-59593-622-6 [contents]
Reference Works
- 2016
- [r3]Andrew A. Kennings, Igor L. Markov:
Circuit Placement. Encyclopedia of Algorithms 2016: 301-306 - 2008
- [r2]Andrew A. Kennings, Igor L. Markov:
Circuit Placement. Encyclopedia of Algorithms 2008 - [r1]Andrew A. Kennings, Kristofer Vorwerk:
Force-Directed and Other Continuous Placement Methods. Handbook of Algorithms for Physical Design Automation 2008
Informal and Other Publications
- 2018
- [i1]Andrew A. Kennings:
Simple FPGA routing graph compression. CoRR abs/1811.04749 (2018)
Coauthor Index
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