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ORCIDJim D. Garside
James Garside
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- affiliation: University of Manchester, UK
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2020 – today
- 2021
[i4]Sebastian Höppner, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Marco Stolba, Florian Kelber, Bernhard Vogginger, Felix Neumärker, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Thomas Hocker, Dennis Walter, Gengting Liu, Jim D. Garside, Steve B. Furber, Christian Mayr:
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. CoRR abs/2103.08392 (2021)- 2020
- [j21]Luis A. Plana
, Jim D. Garside, Jonathan Heathcote, Jeffrey Pepper, Steve Temple, Simon Davidson, Mikel Luján, Steve B. Furber:
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System. IEEE Access 8: 84918-84928 (2020) - [j20]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks. Simul. Model. Pract. Theory 103: 102088 (2020)
2010 – 2019
- 2019
- [j19]Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr:
Dynamic Power Management for Neuromorphic Many-Core Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2973-2986 (2019) - [i3]Sebastian Höppner, Bernhard Vogginger, Yexin Yan, Andreas Dixius, Stefan Scholze, Johannes Partzsch, Felix Neumaerker, Stephan Hartmann, Stefan Schiefer, Georg Ellguth, Love Cederstroem, Luis A. Plana, Jim D. Garside, Steve B. Furber, Christian Mayr:
Dynamic Power Management for Neuromorphic Many-Core Systems. CoRR abs/1903.08941 (2019) - 2018
- [j18]Robert James, Jim D. Garside, Luis A. Plana, Andrew Rowley, Steve B. Furber:
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application. IEEE Trans. Biomed. Circuits Syst. 12(5): 1018-1026 (2018) - [c58]Mantas Mikaitis, David R. Lester, Delong Shang, Steve B. Furber, Gengting Liu, Jim D. Garside, Stefan Scholze, Sebastian Höppner, Andreas Dixius:
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. ARITH 2018: 37-44 - [c57]Anuj Vaishnav, Khoa Dang Pham, Dirk Koch, James Garside:
Resource Elastic Virtualization for FPGAs Using OpenCL. FPL 2018: 111-118 - 2017
- [j17]Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang:
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3152-3165 (2017) - [c56]Robert James, Jim D. Garside, Michael Hopkins, Luis A. Plana, Steve Temple, Simon Davidson, Steve B. Furber:
Parallel distribution of an inner hair cell and auditory nerve model for real-time application. BioCAS 2017: 1-4 - [c55]Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch:
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL 2017: 1-8 - [c54]Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Prateek Joshi, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber:
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS 2017: 1 - [c53]Sebastian Höppner, Yexin Yan, Bernhard Vogginger, Andreas Dixius, Johannes Partzsch, Felix Neumärker, Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Georg Ellguth, Love Cederstroem, Matthias Eberlein, Christian Mayr, Steve Temple, Luis A. Plana, Jim D. Garside, Simon Davidson, David R. Lester, Steve B. Furber:
Dynamic voltage and frequency scaling for neuromorphic many-core systems. ISCAS 2017: 1-4 - [c52]Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján:
Low overhead dynamic binary translation on ARM. PLDI 2017: 333-346 - [c51]Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, John Goodacre, Mikel Luján:
HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation. VEE 2017: 228-241 - 2016
- [j16]Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján:
Optimizing Indirect Branches in Dynamic Binary Translators. ACM Trans. Archit. Code Optim. 13(1): 7:1-7:25 (2016) - [c50]Mahdi Jelodari Mamaghani, Danil Sokolov, Jim D. Garside:
Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis. ACSD 2016: 104-113 - [c49]Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside:
Automatic Clock: A Promising Approach toward GALSification. ASYNC 2016: 83-84 - [c48]Wei Song, Dirk Koch, Mikel Luján, Jim D. Garside:
Parallel Hardware Merge Sorter. FCCM 2016: 95-102 - [c47]Andrew Mundy, Jonathan Heathcote, Jim D. Garside:
On-chip order-exploiting routing table minimization for a multicast supercomputer network. HPSR 2016: 148-154 - [c46]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
HAPPY: Hybrid Address-based Page Policy in DRAMs. MEMSYS 2016: 311-321 - [c45]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. MEMSYS 2016: 362-373 - 2015
- [j15]Andrew D. Brown, Stephen B. Furber, Jeffrey S. Reeve, Jim D. Garside, Kier J. Dugan, Luis A. Plana, Steve Temple:
SpiNNaker - Programming Model. IEEE Trans. Computers 64(6): 1769-1782 (2015) - [c44]Guangda Zhang, Jim D. Garside, Wei Song, Javier Navaridas, Zhiying Wang:
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. ASYNC 2015: 100-107 - [c43]Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards:
De-elastisation: from asynchronous dataflows to synchronous circuits. DATE 2015: 273-276 - [c42]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. FCCM 2015: 96 - [c41]Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Analysis of FPGA and software approaches to simulate unconventional computer architectures. ReConFig 2015: 1-8 - [i2]Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján:
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. CoRR abs/1509.03721 (2015) - [i1]Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján:
HAPPY: Hybrid Address-based Page Policy in DRAMs. CoRR abs/1509.03740 (2015) - 2014
- [j14]Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang:
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. Microprocess. Microsystems 38(8): 826-842 (2014) - [c40]Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang:
An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults. ASYNC 2014: 9-16 - [c39]Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards:
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA. DSD 2014: 607-614 - [c38]Wei Song, Guangda Zhang, Jim D. Garside:
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip. ACM Great Lakes Symposium on VLSI 2014: 211-216 - [c37]Wei Song, Jim D. Garside, Doug A. Edwards:
Automatic data path extraction in large-scale register-transfer level designs. ISCAS 2014: 377-380 - 2013
- [j13]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R. Lester, Andrew D. Brown, Steve B. Furber:
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation. IEEE J. Solid State Circuits 48(8): 1943-1953 (2013) - [j12]Javier Navaridas, Steve B. Furber, Jim D. Garside, Xin Jin, Mukaram M. Khan, David R. Lester, Mikel Luján, José Miguel-Alonso, Eustace Painkras, Cameron Patterson, Luis A. Plana, Alexander D. Rast, Dominic Richards, Yebin Shi, Steve Temple, Jian Wu, Shufan Yang:
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture. Parallel Comput. 39(11): 693-708 (2013) - [j11]Steve B. Furber, David R. Lester, Luis A. Plana, Jim D. Garside, Eustace Painkras, Steve Temple, Andrew D. Brown:
Overview of the SpiNNaker System Architecture. IEEE Trans. Computers 62(12): 2454-2467 (2013) - [c36]Guangda Zhang, Wei Song, Jim D. Garside, Javier Navaridas, Zhiying Wang:
Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. DSD 2013: 3-10 - [c35]Wei Song, Jim D. Garside:
Automatic Controller Detection for Large Scale RTL Designs. DSD 2013: 844-851 - 2012
- [j10]Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve B. Furber:
Scalable communications for a million-core neural processing architecture. J. Parallel Distributed Comput. 72(11): 1507-1520 (2012) - [c34]Geoffrey Ndu, Jim D. Garside:
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. ARC 2012: 114-125 - [c33]Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana:
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC 2012: 49-56 - [c32]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve B. Furber:
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4 - [c31]Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge:
Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE 2012: 1495-1500 - 2011
- [j9]Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge:
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7(4): 17:1-17:18 (2011)
2000 – 2009
- 2009
- [c30]Jian Wu, Steve B. Furber, Jim D. Garside:
A Programmable Adaptive Router for a GALS Parallel System. ASYNC 2009: 23-31 - [c29]Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana:
Fault Tolerant Delay Insensitive Inter-chip Communication. ASYNC 2009: 77-84 - [c28]Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods:
The Amulet chips: Architectural development for asynchronous microprocessors. ICECS 2009: 343-346 - 2008
- [c27]Konstantinos Nikas, Matthew Horsnell, Jim D. Garside:
An adaptive bloom filter cache partitioning scheme for multicore architectures. ICSAMOS 2008: 25-32 - 2007
- [c26]Andrew Robinson, Jim D. Garside:
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ACM Great Lakes Symposium on VLSI 2007: 138-143 - 2006
- [j8]Saeid Nooshabadi, Jim D. Garside:
Modernization of teaching in embedded systems design - an international collaborative project. IEEE Trans. Educ. 49(2): 254-262 (2006) - 2005
- [c25]Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou:
A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190 - [c24]Charlie Brej, Jim D. Garside:
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373 - 2004
- [j7]Aristides Efthymiou, Jim D. Garside:
A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 325-329 (2004) - [c23]Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury:
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215 - 2003
- [j6]Luis A. Plana, Peter A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu:
SPA - a secure Amulet core for smartcard applications. Microprocess. Microsystems 27(9): 431-446 (2003) - [j5]Daranee Hormdee, Jim D. Garside, Stephen B. Furber:
An asynchronous copy-back cache architecture. Microprocess. Microsystems 27(10): 485-500 (2003) - [c22]Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55 - 2002
- [c21]W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Peter A. Riocreux, Luis A. Plana:
SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210 - [c20]Daranee Hormdee, Jim D. Garside, Stephen B. Furber:
An Asynchronous Victim Cache. DSD 2002: 4-11 - [c19]Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457 - [c18]Aristides Efthymiou, Jim D. Garside:
An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141 - [c17]Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside:
Logic Design of Asynchronous Circuits (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 26- - 2001
- [j4]Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple:
Power Management in the Amulet Microprocessors. IEEE Des. Test Comput. 18(2): 42-52 (2001) - [c16]David W. Lloyd, Jim D. Garside:
A Practical Comparison of Asynchronous Design Styles. ASYNC 2001: 36-45 - [c15]Daranee Hormdee, Jim D. Garside:
AMULET3i Cache Architecture. ASYNC 2001: 152-161 - 2000
- [c14]Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli:
AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175 - [c13]Stephen B. Furber, David A. Edwards, Jim D. Garside:
AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD 2000: 329-334
1990 – 1999
- 1999
- [j3]Stephen B. Furber, James Garside, Peter A. Riocreux, Steve Temple, Paul Day, Jianwei Liu, Nigel C. Paver:
AMULET2e: an asynchronous embedded controller. Proc. IEEE 87(2): 243-256 (1999) - [c12]Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury:
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC 1999: 27-35 - [c11]Jim D. Garside, Stephen B. Furber, S.-H. Chung:
AMULET3 Revealed. ASYNC 1999: 51-59 - [c10]David W. Lloyd, Jim D. Garside, D. A. Gilbert:
Memory Faults in Asynchronous Microprocessors. ASYNC 1999: 71- - 1998
- [j2]Stephen B. Furber, Jim D. Garside, Steve Temple, Paul Day, Nigel C. Paver:
Asynchronous Embedded Control. Integr. Comput. Aided Eng. 5(1): 57-68 (1998) - [c9]Stephen B. Furber, Jim D. Garside, D. A. Gilbert:
AMULET3: a high-performance self-timed ARM microprocessor. ICCD 1998: 247-252 - 1997
- [j1]John V. Woods, Paul Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple:
AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46(4): 385-398 (1997) - [c8]D. A. Gilbert, Jim D. Garside:
A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC 1997: 2-11 - [c7]Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver:
AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290- - 1996
- [c6]Jim D. Garside, Steve Temple, Rahul Mehra:
The AMULET2e cache system. ASYNC 1996: 208-217 - 1994
- [c5]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods:
AMULET1: A Micropipelined ARM. COMPCON 1994: 476-485 - [c4]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods:
The Design and Evaluation of an Asynchronous Microprocessor. ICCD 1994: 217-220 - 1993
- [c3]Jim D. Garside:
A CMOS VLSI Implementation of an Asynchronous ALU. Asynchronous Design Methodologies 1993: 181-192 - [c2]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods:
A micropipelined ARM. VLSI 1993: 211-220 - 1992
- [c1]N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods:
Register Locking in an Asynchronous Microprocessor. ICCD 1992: 351-355
Coauthor Index
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