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ORCIDDajiang Zhou
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- affiliation (PhD 2010): Waseda University, Kitakyushu, Japan
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2020 – today
- 2024
[c65]Tianxiao Gao, Li Guo, Shanwei Zhao, Peihan Xu, Yukun Yang, Xionghao Liu, Shihao Wang, Shiai Zhu, Dajiang Zhou:
QuantNAS: Quantization-aware Neural Architecture Search For Efficient Deployment On Mobile Device. CVPR Workshops 2024: 1704-1713- 2023
- [c64]Marcos V. Conde, Eduard Zamfir, Radu Timofte
, Daniel Motilla, Cen Liu, Zexin Zhang, Yunbo Peng, Yue Lin, Jiaming Guo, Xueyi Zou, Yuyi Chen, Yi Liu, Jia Hao, Youliang Yan, Yuanfan Zhang, Gen Li, Lei Sun, Lingshun Kong, Haoran Bai, Jinshan Pan, Jiangxin Dong, Jinhui Tang, Mustafa Ayazoglu, Bahri Batuhan Bilecen, Mingxi Li, Yuhang Zhang, Xianjun Fan, Yankai Sheng, Long Sun, Zibin Liu, Weiran Gou, Shaoqing Li, Ziyao Yi, Yan Xiang, Dehui Kong, Ke Xu, Ganzorig Gankhuyag, Kihwan Yoon, Jin Zhang, Gaocheng Yu, Feng Zhang, Hongbin Wang, Zhou Zhou, Jiahao Chao, Hongfan Gao, Jiali Gong, Zhengfeng Yang, Zhenbing Zeng, Chengpeng Chen, Zichao Guo, Anjin Park, Yuqing Liu, Qi Jia, Hongyuan Yu, Xuanwu Yin, Dongyang Zhang, Ting Fu, Zhengxue Cheng, Shiai Zhu, Dajiang Zhou, Weichen Yu, Lin Ge, Jiahua Dong, Yajun Zou, Zhuoyuan Wu, Binnan Han, Xiaolin Zhang, Heng Zhang, Ben Shao, Shaolong Zheng, Daheng Yin, Baijun Chen, Mengyang Liu, Marian-Sergiu Nistor, Yi-Chung Chen, Zhi-Kai Huang, Yuan-Chun Chiang, Wei-Ting Chen, Hao-Hsiang Yang, Hua-En Chang, I-Hsiang Chen, Chia-Hsuan Hsieh, Sy-Yen Kuo, Tu Vo, Qingsen Yan, Yun Zhu, Jinqiu Su, Yanning Zhang, Cheng Zhang, Jiaying Luo, Youngsun Cho, Nakyung Lee, Kunlong Zuo:
Efficient Deep Models for Real-Time 4K Image Super-Resolution. NTIRE 2023 Benchmark and Report. CVPR Workshops 2023: 1495-1521 - [c63]Hanqing Zhu, Dajiang Zhou, Zhongyu Li, Hongyang An, Chuan Huang, Yun Zhou, Jianyu Yang:
Moving Target Detection Method for Passive Radar Using LEO Communication Satellite Constellation. IGARSS 2023: 8090-8093 - [c62]Dajiang Zhou, Hanqing Zhu, Yulin Huang, Yongchao Zhang, Jianyu Yang, Qingying Yi:
A High Resolution SAR Imaging Method for Moving Target Based on Range Doppler and Particle Swarm Optimization Algorithm. IGARSS 2023: 8261-8264 - 2021
- [c61]Zhengxue Cheng, Ting Fu, Jiapeng Hu, Li Guo, Shihao Wang, Xiongxin Zhao, Dajiang Zhou, Yang Song:
Perceptual Image Compression Using Relativistic Average Least Squares GANs. CVPR Workshops 2021: 1895-1900
2010 – 2019
- 2018
- [j46]Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, Satoshi Goto:
Lossy Compression for Embedded Computer Vision Systems. IEEE Access 6: 39385-39397 (2018) - [j45]Jian-Bin Zhou, Dajiang Zhou, Takeshi Yoshimura, Satoshi Goto:
Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing. IEICE Trans. Electron. 101-C(4): 263-272 (2018) - [j44]Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto:
A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. IEEE Trans. Circuits Syst. Video Technol. 28(2): 556-560 (2018) - [c60]Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura:
Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. ASP-DAC 2018: 184-189 - [c59]Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura:
Embedded Frame Compression for Energy-Efficient Computer Vision Systems. ISCAS 2018: 1-5 - [c58]Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura:
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. ISCAS 2018: 1-5 - 2017
- [j43]Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura:
Accelerating HEVC Inter Prediction with Improved Merge Mode Handling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 546-554 (2017) - [j42]Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor. IEICE Trans. Electron. 100-C(3): 223-231 (2017) - [j41]Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2416-2424 (2017) - [j40]Jian-Bin Zhou, Dajiang Zhou, Li Guo, Takeshi Yoshimura, Satoshi Goto:
Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2869-2877 (2017) - [j39]Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto:
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE J. Solid State Circuits 52(1): 113-126 (2017) - [j38]Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto:
VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications. IEEE Trans. Circuits Syst. Video Technol. 27(2): 380-393 (2017) - [j37]Heming Sun, Dajiang Zhou, Landan Hu, Shinji Kimura, Satoshi Goto:
Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. IEEE Trans. Multim. 19(11): 2375-2390 (2017) - [j36]Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Shuping Zhang, Takeshi Yoshimura, Satoshi Goto:
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 714-724 (2017) - [c57]Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura:
Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. DATE 2017: 1032-1037 - [c56]Jian-Bin Zhou, Dajiang Zhou, Li Guo, Takeshi Yoshimura, Satoshi Goto:
Measurement-domain intra prediction framework for compressively sensed images. ISCAS 2017: 1-4 - [c55]Jian-Bin Zhou, Dajiang Zhou, Takeshi Yoshimura, Satoshi Goto:
Approximate-DCT-derived measurement matrices for compressed sensing. ISCAS 2017: 1-4 - [c54]Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
100x Evolution of Video Codec Chips. ISPD 2017: 121-122 - [i3]Shihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura:
Chain-NN: An Energy-Efficient 1D Chain Architecture for Accelerating Deep Convolutional Neural Networks. CoRR abs/1703.01457 (2017) - [i2]Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura:
CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks. CoRR abs/1703.07348 (2017) - 2016
- [j35]Zhenqi Wei, Peilin Liu, Rongdi Sun, Zunquan Zhou, Ke Jin, Dajiang Zhou:
HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip. IEICE Electron. Express 13(14): 20160529 (2016) - [j34]Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura:
A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2375-2387 (2016) - [c53]Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura:
CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. ICCD 2016: 320-327 - [c52]Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. ICME Workshops 2016: 1-6 - [c51]Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto:
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. ISSCC 2016: 266-268 - [i1]Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. CoRR abs/1605.02976 (2016) - 2015
- [j33]Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto:
Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1356-1365 (2015) - [j32]Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Low-Power Motion Estimation Processor with 3D Stacked Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1431-1441 (2015) - [j31]Jian-Bin Zhou, Dajiang Zhou, Shihao Wang, Takeshi Yoshimura, Satoshi Goto:
High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2519-2527 (2015) - [j30]Dajiang Zhou, Jinjia Zhou, Wei Fei, Satoshi Goto:
Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications. IEEE Trans. Circuits Syst. Video Technol. 25(3): 497-507 (2015) - [j29]Jinjia Zhou, Dajiang Zhou, Jiayi Zhu, Satoshi Goto:
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2768-2781 (2015) - [j28]Gang He, Dajiang Zhou, Yunsong Li, Zhixiang Chen, Tianruo Zhang, Satoshi Goto:
High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3138-3142 (2015) - [c50]Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou:
A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. ASICON 2015: 1-4 - [c49]Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura:
Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder. ICME Workshops 2015: 1-6 - [c48]Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
An independent bandwidth reduction device for HEVC VLSI video system. ISCAS 2015: 609-612 - [c47]Jinjia Zhou, Yizhou Zou, Dajiang Zhou, Satoshi Goto:
A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio. ISCAS 2015: 617-620 - [c46]Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura:
Merge mode based fast inter prediction for HEVC. VCIP 2015: 1-4 - 2014
- [j27]Heming Sun, Dajiang Zhou, Peilin Liu, Satoshi Goto:
Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2): 510-519 (2014) - [j26]Heming Sun, Dajiang Zhou, Peilin Liu, Satoshi Goto:
A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2467-2476 (2014) - [j25]Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2488-2497 (2014) - [j24]Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto:
A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder. IEEE J. Solid State Circuits 49(4): 827-837 (2014) - [j23]Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC. J. Vis. Commun. Image Represent. 25(5): 1275-1286 (2014) - [j22]Li Guo, Dajiang Zhou, Satoshi Goto:
A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec. IEEE Trans. Multim. 16(8): 2323-2332 (2014) - [j21]Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto:
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 76-89 (2014) - [c45]Haoming Zhang, Dajiang Zhou, Satoshi Goto:
Live demonstration: FPGA based 3840×2160 video decoding and displaying system. APCCAS 2014: 169-170 - [c44]Fan Wang, Dajiang Zhou, Satoshi Goto:
OpenCL based high-quality HEVC motion estimation on GPU. ICIP 2014: 1263-1267 - [c43]Yijin Zhao, Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications. ICIP 2014: 1268-1272 - [c42]Jian-Bin Zhou, Dajiang Zhou, Heming Sun, Satoshi Goto:
VLSI architecture of HEVC intra prediction for 8K UHDTV applications. ICIP 2014: 1273-1277 - [c41]Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto:
Fast SAO estimation algorithm and its VLSI architecture. ICIP 2014: 1278-1282 - [c40]Dajiang Zhou, Li Guo, Jinjia Zhou, Satoshi Goto:
Reducing power consumption of HEVC codec with lossless reference frame recompression. ICIP 2014: 2120-2124 - [c39]Shihao Wang, Dajiang Zhou, Satoshi Goto:
Motion compensation architecture for 8K UHDTV HEVC decoder. ICME 2014: 1-6 - [c38]Zhe Sheng, Dajiang Zhou, Heming Sun, Satoshi Goto:
Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction. MMM (1) 2014: 541-552 - [c37]Shihao Wang, Dajiang Zhou, Jian-Bin Zhou, Takeshi Yoshimura, Satoshi Goto:
Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder. PCM 2014: 74-83 - [c36]Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto:
An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. VCIP 2014: 197-200 - [c35]Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
A low power 720p motion estimation processor with 3D stacked memory. VLSI-SoC 2014: 1-6 - 2013
- [j20]Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto:
A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1366-1375 (2013) - [j19]Jiayi Zhu, Dajiang Zhou, Satoshi Goto:
A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2612-2622 (2013) - [j18]Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2623-2632 (2013) - [c34]Gang He, Dajiang Zhou, Satoshi Goto:
Transform-based fast mode and depth decision algorithm for HEVC intra prediction. ASICON 2013: 1-4 - [c33]Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto:
A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. ASP-DAC 2013: 73-74 - [c32]Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto:
A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. ASP-DAC 2013: 87-88 - [c31]Li Guo, Dajiang Zhou, Satoshi Goto:
Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec. EUSIPCO 2013: 1-5 - [c30]Jinjia Zhou, Dajiang Zhou, Wei Fei, Satoshi Goto:
A high-performance CABAC encoder architecture for HEVC and H.264/AVC. ICIP 2013: 1568-1572 - [c29]Jiayi Zhu, Dajiang Zhou, Gang He, Satoshi Goto:
A combined SAO and de-blocking filter architecture for HEVC video decoder. ICIP 2013: 1967-1971 - [c28]Yue Pan, Dajiang Zhou, Satoshi Goto:
An FPGA-based 4K UHDTV H.264/AVC video decoder. ICME Workshops 2013: 1-4 - [c27]Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
High-parallel performance-aware LDPC decoder IP core design for WiMAX. MWSCAS 2013: 1136-1139 - 2012
- [j17]Xiongxin Zhao, Xiao Peng, Zhixiang Chen, Dajiang Zhou, Satoshi Goto:
A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2384-2391 (2012) - [j16]Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
DVB-T2 LDPC Decoder with Perfect Conflict Resolution. Inf. Media Technol. 7(2): 584-592 (2012) - [j15]Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
DVB-T2 LDPC Decoder with Perfect Conflict Resolution. IPSJ Trans. Syst. LSI Des. Methodol. 5: 23-31 (2012) - [j14]Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto:
An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding. IEEE Trans. Multim. 14(2): 237-249 (2012) - [c26]Gang He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder. EUSIPCO 2012: 1054-1058 - [c25]Zhengyan Guo, Dajiang Zhou, Satoshi Goto:
An optimized MC interpolation architecture for HEVC. ICASSP 2012: 1117-1120 - [c24]Jinjia Zhou, Dajiang Zhou, Satoshi Goto:
Interlaced asymmetric search range assignment for bidirectional motion estimation. ICIP 2012: 1557-1560 - [c23]Heming Sun, Dajiang Zhou, Satoshi Goto:
A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering. ICME 2012: 1085-1090 - [c22]Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto:
A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. ISSCC 2012: 224-226 - [c21]Muchen Li, Jinjia Zhou, Dajiang Zhou, Xiao Peng, Satoshi Goto:
De-blocking Filter Design for HEVC and H.264/AVC. PCM 2012: 273-284 - [c20]Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
DVB-T2 LDPC decoder with perfect conflict resolution. VLSI-DAT 2012: 1-4 - [c19]Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto:
A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. VLSIC 2012: 154-155 - 2011
- [j13]Gang He, Dajiang Zhou, Jinjia Zhou, Tianruo Zhang, Satoshi Goto:
A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. IEICE Trans. Electron. 94-C(4): 419-427 (2011) - [j12]Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto:
Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. IEICE Trans. Electron. 94-C(4): 439-447 (2011) - [j11]Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto:
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2587-2596 (2011) - [j10]Xun He, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto:
A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2609-2618 (2011) - [j9]Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto:
A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip. IEEE J. Solid State Circuits 46(4): 777-788 (2011) - [c18]Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto:
A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. A-SSCC 2011: 317-320 - [c17]Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto:
A 16-65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications. EUSIPCO 2011: 729-733 - [c16]Wei Fei, Dajiang Zhou, Satoshi Goto:
A 1 Gbin/s CABAC encoder for H.264/AVC. EUSIPCO 2011: 1524-1528 - [c15]Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto:
A 98 GMACs/W 32-core vector processor in 65nm CMOS. ISLPED 2011: 373-378 - [c14]Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto:
A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. SiPS 2011: 122-127 - [c13]Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto:
Ultra low power QC-LDPC decoder with high parallelism. SoCC 2011: 142-145 - 2010
- [j8]Xianmin Chen, Peilin Liu, Dajiang Zhou, Jiayi Zhu, Xingguang Pan, Satoshi Goto:
A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. IEICE Trans. Electron. 93-C(3): 253-260 (2010) - [j7]Jinjia Zhou, Dajiang Zhou, Xun He, Satoshi Goto:
A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(8): 1425-1433 (2010) - [j6]Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto:
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. Inf. Media Technol. 5(4): 1156-1166 (2010) - [j5]Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
High Profile Intra Prediction Architecture for UHD H.264 Decoder. Inf. Media Technol. 5(4): 1167-1177 (2010) - [j4]Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto:
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. IPSJ Trans. Syst. LSI Des. Methodol. 3: 292-302 (2010) - [j3]Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
High Profile Intra Prediction Architecture for UHD H.264 Decoder. IPSJ Trans. Syst. LSI Des. Methodol. 3: 303-313 (2010) - [c12]Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto:
A constant rate bandwidth reduction architecture with adaptive compression mode decision for video decoding. EUSIPCO 2010: 2017-2021 - [c11]Xuena Bao, Dajiang Zhou, Peilin Liu, Satoshi Goto:
An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding. ICME 2010: 820-825 - [c10]Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto, Peilin Liu:
An adaptive bandwidth reduction scheme for video coding. ISCAS 2010: 401-404 - [c9]Zhixiang Chen, Xiongxin Zhao, Xiao Peng, Dajiang Zhou, Satoshi Goto:
An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. ISCAS 2010: 473-476 - [c8]Xuena Bao, Dajiang Zhou, Satoshi Goto:
A lossless frame recompression scheme for reducing DRAM power in video encoding. ISCAS 2010: 677-680 - [c7]Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto:
A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. PCM (2) 2010: 52-61 - [c6]Gang He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
Intra prediction architecture for H.264/AVC QFHD encoder. PCS 2010: 450-453
2000 – 2009
- 2009
- [j2]Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(8): 1978-1985 (2009) - [j1]Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Satoshi Goto:
A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3203-3210 (2009) - [c5]Jinjia Zhou, Dajiang Zhou, Hang Zhang, Yu Hong, Peilin Liu, Satoshi Goto:
A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications. ICME 2009: 1134-1137 - [c4]Xianmin Chen, Peilin Liu, Jiayi Zhu, Dajiang Zhou, Satoshi Goto:
Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder. ISCAS 2009: 1069-1072 - [c3]Dajiang Zhou, Jinjia Zhou, Satoshi Goto:
Prioritized Reference Decision for Efficient Motion Vector Coding. ISCAS 2009: 1649-1652 - 2008
- [c2]Jiayi Zhu, Peilin Liu, Dajiang Zhou:
An SDRAM controller optimized for high definition video coding application. ISCAS 2008: 3518-3521 - 2007
- [c1]Dajiang Zhou, Peilin Liu:
A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. ISCAS 2007: 2910-2913
Coauthor Index
[j46] [j45] [j44] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [c56] [c55] [c54] [c52] [c51] [i1] [j33] [j32] [j31] [j30] [j29] [j28] [c48] [c47] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [j20] [j19] [j18] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [j17] [j16] [j15] [j14] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j13] [j12] [j11] [j10] [j9] [c18] [c17] [c16] [c15] [c14] [c13] [j8] [j7] [j6] [j5] [j4] [j3] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [j2] [j1] [c5] [c4] [c3]
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