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ORCIDDae Hyun Kim 0004
Person information
- affiliation: Washington State University (WSU), School of Electrical Engineering and Computer Science, Pullman, WA, USA
- affiliation (PhD 2012): Georgia Institute of Technology, Atlanta, GA, USA
Other persons with the same name
- Daehyun Kim (aka: Dae Hyun Kim, Dae-Hyun Kim) — disambiguation page
- Dae-Hyun Kim 0003
![[0000-0003-0801-0230]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0003-0801-0230")
(aka: Dae Hyun Kim 0003, Daehyun Kim 0003) — Samsung Electronics, Hwaseong, Korea (and 1 more) - Daehyun Kim 0005 (aka: Dae Hyun Kim 0005) — Stanford University, Tableau Research, CA, USA
- Daehyun Kim 0006 (aka: Dae Hyun Kim 0006) — University of Illinois at Urbana-Champaign, Department of Aerospace Engineering, IL, USA
- Daehyun Kim 0001 — Intel Corporation, Santa Clara, CA, USA
- Daehyun Kim 0002 — Georgia Institute of Technology, GA, USA
- Daehyun Kim 0007 — UCLA, Department of Economics Los Angeles, CA, USA
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2020 – today
- 2024
[j23]Monzurul Islam Dewan, Sheng-En David Lin, Dae Hyun Kim:
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. ACM Trans. Design Autom. Electr. Syst. 29(1): 17:1-17:28 (2024)- 2023
- [c29]Jihee Seo, Dae-Hyun Kim:
Dual-Purpose Hardware Algorithms and Architectures - Part 2: Integer Division. ARITH 2023: 1-8 - [c28]Jihee Seo, Dae-Hyun Kim:
Dual-Purpose Hardware Algorithms and Architectures - Part 1: Floating-Point Division. ARITH 2023: 24-31 - 2022
- [j22]Edward Lee, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay:
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process. ACM J. Emerg. Technol. Comput. Syst. 18(1): 20:1-20:20 (2022) - [j21]Monzurul Islam Dewan, Dae Hyun Kim:
Design Automation Algorithms for the NP-Separate VLSI Design Methodology. ACM Trans. Design Autom. Electr. Syst. 27(5): 53:1-53:20 (2022) - [c27]Aryan Deshwal, Syrine Belakaria, Janardhan Rao Doppa, Dae Hyun Kim:
Bayesian Optimization over Permutation Spaces. AAAI 2022: 6515-6523 - 2021
- [j20]Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration. ACM Trans. Design Autom. Electr. Syst. 26(2): 16:1-16:21 (2021) - [i3]Aryan Deshwal, Syrine Belakaria, Janardhan Rao Doppa, Dae Hyun Kim:
Bayesian Optimization over Permutation Spaces. CoRR abs/2112.01049 (2021) - 2020
- [j19]Sheng-En David Lin, Dae Hyun Kim:
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1165-1176 (2020) - [j18]Monzurul Islam Dewan, Dae Hyun Kim:
NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5111-5122 (2020) - [j17]Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Partha Pratim Pande:
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 686-699 (2020) - [c26]Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips. DATE 2020: 1752-1757 - [c25]Jinwoo Kim, Gauthaman Murali, Pruek Vanna-Iampikul, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, Sung Kyu Lim:
RTL-to-GDS Design Tools for Monolithic 3D ICs. ICCAD 2020: 126:1-126:8 - [i2]Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration. CoRR abs/2012.00102 (2020)
2010 – 2019
- 2019
- [j16]Sheng-En David Lin, Dae Hyun Kim:
Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs. IEEE Trans. Emerg. Top. Comput. 7(2): 301-310 (2019) - [c24]Jihee Seo, Dae Hyun Kim:
High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding. ARITH 2019: 143-150 - [c23]Jihee Seo, Dae Hyun Kim:
Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers. DATE 2019: 924-927 - [c22]Sheng-En David Lin, Dae Hyun Kim:
Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing. ISPD 2019: 57-64 - [c21]Shantonu Das, Dae Hyun Kim:
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design. ISQED 2019: 323-328 - [c20]Sheng-En David Lin, Dae Hyun Kim:
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits. ISQED 2019: 329-334 - [i1]Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Partha Pratim Pande:
Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures. CoRR abs/1906.04293 (2019) - 2018
- [j15]Dongjin Lee, Sourav Das, Dae Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande:
Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach. ACM J. Emerg. Technol. Comput. Syst. 14(3): 32:1-32:26 (2018) - [j14]Sheng-En David Lin, Dae Hyun Kim:
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 845-854 (2018) - [j13]Inki Hong, Dae Hyun Kim:
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1614-1626 (2018) - [c19]Sheng-En David Lin, Dae Hyun Kim:
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid. ISPD 2018: 18-25 - 2017
- [c18]Yiting Chen, Dae Hyun Kim:
A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits. ISQED 2017: 277-282 - 2016
- [j12]Daehyun Kim, Sung Kyu Lim:
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2. IEEE Des. Test 33(2): 7-8 (2016) - [c17]Sheng-En David Lin, Partha Pratim Pande, Dae Hyun Kim:
Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs. ISQED 2016: 29-34 - 2015
- [j11]Dae Hyun Kim, Sung Kyu Lim:
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools. IEEE Des. Test 32(4): 6-7 (2015) - [j10]Dae Hyun Kim, Sung Kyu Lim:
Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities. IEEE Des. Test 32(4): 8-22 (2015) - [j9]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - [c16]Sourav Das, Dongjin Lee, Dae Hyun Kim, Partha Pratim Pande:
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures. ACM Great Lakes Symposium on VLSI 2015: 133-138 - [c15]Sourav Das, Janardhan Rao Doppa, Daehyun Kim, Partha Pratim Pande, Krishnendu Chakrabarty:
Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach. ICCAD 2015: 705-712 - 2014
- [j8]Chang-Chih Chen, Muhammad Bashir, Linda S. Milor, Daehyun Kim, Sung Kyu Lim:
Simulation of system backend dielectric reliability. Microelectron. J. 45(10): 1327-1334 (2014) - [j7]Daehyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim:
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1384-1395 (2014) - [j6]Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, Sung Kyu Lim:
Backend Dielectric Reliability Full Chip Simulator. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1750-1762 (2014) - 2013
- [j5]Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim:
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 862-874 (2013) - [c14]Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim:
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. ASP-DAC 2013: 687-692 - 2012
- [j4]Dae Hyun Kim, Sung Kyu Lim:
Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 240-248 (2012) - [j3]Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, Linda Milor:
Backend dielectric reliability simulator for microprocessor system. Microelectron. Reliab. 52(9-10): 1953-1959 (2012) - [c13]Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim:
Block-level 3D IC design with through-silicon-via planning. ASP-DAC 2012: 335-340 - [c12]Kaiyuan Yang, Dae Hyun Kim, Sung Kyu Lim:
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices. ISQED 2012: 740-746 - [c11]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - 2011
- [j2]Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim:
Impact of irregular geometries on low-k dielectric breakdown. Microelectron. Reliab. 51(9-11): 1582-1586 (2011) - [c10]Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim:
TSV density-driven global placement for 3D stacked ICs. ISOCC 2011: 135-138 - [c9]Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon:
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ISQED 2011: 122-128 - [c8]Daehyun Kim, Suyoun Kim, Sung Kyu Lim:
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs. SLIP 2011: 1-8 - 2010
- [j1]Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim:
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. Microelectron. Reliab. 50(9-11): 1341-1346 (2010) - [c7]Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim:
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4 - [c6]Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay:
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. ICCAD 2010: 694-697 - [c5]Daehyun Kim, Sung Kyu Lim:
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. SLIP 2010: 25-32
2000 – 2009
- 2009
- [c4]Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim:
A study of Through-Silicon-Via impact on the 3D stacked IC layout. ICCAD 2009: 674-680 - [c3]Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim:
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. SLIP 2009: 85-92 - 2008
- [c2]Dae Hyun Kim, Sung Kyu Lim:
Bus-aware microarchitectural floorplanning. ASP-DAC 2008: 204-208 - [c1]Dae Hyun Kim, Sung Kyu Lim:
Global bus route optimization with application to microarchitectural design exploration. ICCD 2008: 658-663
Coauthor Index
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last updated on 2024-04-18 20:33 CEST by the dblp team
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