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ORCIDICCAD 2012: San Jose, California, USA
- Alan J. Hu:
2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012. ACM 2012, ISBN 978-1-4577-1398-9 - Xue Lin, Yanzhi Wang, Di Zhu, Naehyuck Chang, Massoud Pedram:
Online fault detection and tolerance for photovoltaic energy harvesting systems. 1-6 - Tuck-Boon Chan, Andrew B. Kahng:
Tunable sensors for process-aware voltage scaling. 7-14 - Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Collaborative calibration of on-chip thermal sensors using performance counters. 15-22 - Nathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris
:
Spatial correlation modeling for probe test cost reduction in RF devices. 23-29 - Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker:
Small-delay-fault ATPG with waveform accuracy. 30-36 - Andrew Ferraiuolo, Xuehui Zhang, Mohammad Tehranipoor:
Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC. 37-42 - Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat:
Layout small-angle rotation and shift for EUV defect mitigation. 43-49 - Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta:
A methodology for the early exploration of design rules for multiple-patterning technologies. 50-56 - Haitong Tian, Hongbo Zhang, Qiang Ma, Zigang Xiao, Martin D. F. Wong:
A polynomial time triple patterning algorithm for cell based row-structure layout. 57-64 - Wei Ding, Mahmut T. Kandemir:
Improving last level cache locality by integrating loop and data transformations. 65-72 - Minje Jun, Myoung-Jin Kim, Eui-Young Chung:
Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture. 73-80 - Jishen Zhao, Yuan Xie:
Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration. 81-87 - Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu:
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. 88-94 - Andrew DeOrio, Jialin Li, Valeria Bertacco:
Bridging pre- and post-silicon debugging with BiPeD. 95-100 - Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir:
Novel test detection to improve simulation efficiency - A commercial experiment. 101-108 - Bo-Han Wu, Chung-Yang (Ric) Huang:
A robust general constrained random pattern generator for constraints with variable ordering. 109-114 - Somnath Banerjee, Tushar Gupta:
Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation. 115-122 - Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: A triple patterning lithography aware detailed router. 123-129 - Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Maze routing algorithms with exact matching constraints for analog and mixed signal designs. 130-136 - Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan:
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. 137-143 - Tao Huang, Evangeline F. Y. Young:
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles. 144-151 - He Wen, Laszlo B. Kish:
Noise based logic: Why noise? 152-155 - Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel:
An efficient implementation of numerical integration using logical computation on stochastic bit streams. 156-162 - Hui Geng, Jun Wu, Jianming Liu, Minsu Choi, Yiyu Shi:
Utilizing random noise in cryptography: Where is the Tofu? 163-167 - Hsin Chen, Chih-Cheng Lu, Yi-Da Wu, Tang-Jung Chiu:
Learning from biological neurons to compute with electronic noise special. 168-171 - S. Ramprasath, Vinita Vasudevan:
On the computation of criticality in statistical timing analysis. 172-179 - Wangyang Zhang, Amith Singhee, Jinjun Xiong, Peter A. Habitz, Amol Joshi, Chandu Visweswariah, James Sundquist:
A dynamic method for efficient random mismatch characterization of standard cells. 180-186 - Honghuang Lin, Peng Li:
Classifying circuit performance using active-learning guided support vector machines. 187-194 - Chien-Chih Yu, Armin Alaghi, John P. Hayes:
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo. 195-201 - Sebastian Steinhorst, Lars Hedrich:
Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits. 202-209 - Lingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan:
Word level feature discovery to enhance quality of assertion mining. 210-217 - John Lee, Puneet Gupta:
Impact of range and precision in technology on cell-based design. 218-225 - Li Li, Peng Kang, Yinghai Lu, Hai Zhou:
An efficient algorithm for library-based cell-type selection in high-performance low-power designs. 226-232 - Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-Chul Kim, Igor L. Markov:
Sensitivity-guided metaheuristics for accurate discrete gate sizing. 233-239 - Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan:
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). 240-242 - Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar:
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. 243-246 - Suming Lai, Boyuan Yan, Peng Li:
Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators. 247-254 - Cheng Zhuo, Gustavo R. Wilke, Ritochit Chakraborty, Alaeddin A. Aydiner, Sourav Chakravarty, Wei-Kai Shih:
A silicon-validated methodology for power delivery modeling and simulation. 255-262 - Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar:
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. 263-270 - Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held:
Scaling the "Memory Wall": Designer track. 271-272 - Sandeep Kumar Goel:
Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track. 273 - Robert Patti:
3D integrated circuits: Designing in a new dimension: Designer track. 274 - Igor L. Markov, Jin Hu, Myung-Chul Kim:
Progress and challenges in VLSI placement research. 275-282 - Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? 283-290 - Natasa Miskov-Zivanov, James R. Faeder, Chris J. Myers, Herbert M. Sauro:
Modeling and design automation of biological circuits and systems. 291-293 - Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas:
CACTI-IO: CACTI with off-chip power-area-timing models. 294-301 - Hamed Tabkhi, Gunar Schirner:
AFReP: Application-guided Function-level Registerfile power-gating for embedded processors. 302-308 - Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Hui Geng, Shih-Chieh Chang:
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. 309-316 - Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar:
A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. 317-324 - Jiwoo Pak, Sung Kyu Lim, David Z. Pan:
Electromigration-aware routing for 3D ICs with stress-aware EM modeling. 325-332 - Jianyong Xie, Madhavan Swaminathan:
3D transient thermal solver using non-conformal domain decomposition approach. 333-340 - Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li:
Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. 341 - WoeiTzy Jong, Hwei-Tseng Wang, Chengta Hsieh, Kei-Yong Khoo:
ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest. 342-344 - Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. 345-348 - J. Andres Torres:
ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite. 349-350 - Mian Dong, Tian Lan, Lin Zhong:
System energy consumption is a multi-player game. 351-352 - Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho:
Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips. 353-360 - De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng:
Compiling program control flows into biochemical reactions. 361-368 - Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho:
Dictionary-based error recovery in cyberphysical digital-microfluidic biochips. 369-376 - Juinn-Dar Huang, Chia-Hung Liu, Ting-Wei Chiang:
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees. 377-383 - Konstantis Daloukas, Nestoras E. Evmorfopoulos, George Drasidis, Michalis K. Tsiampas, Panagiota E. Tsompanopoulou, George I. Stamoulis:
Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architectures. 384-391 - Jia Wang:
Deterministic random walk preconditioning for power grid analysis. 392-398 - Ting Yu, Zigang Xiao, Martin D. F. Wong:
Efficient parallel power grid analysis via Additive Schwarz Method. 399-406 - Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng:
Circuit simulation via matrix exponential method for stiffness handling and parallel processing. 407-414 - Pierre-Francois Desrumaux, Yoan Dupret, Jens Tingleff, Sean Minehane, Mark Redford, Laurent Latorre, Pascal Nouet:
An efficient control variates method for yield estimation of analog circuits based on a local model. 415-421 - Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential. 422-428 - Xueqian Zhao, Zhuo Feng:
GPSCP: A general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations. 429-435 - Leyi Yin, Yue Deng, Peng Li:
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques. 436-442 - Richard F. Barrett, Xiaobo Sharon Hu, Sudip S. Dosanjh, Steven G. Parker, Michael A. Heroux, John Shalf:
Toward codesign in high performance computing systems. 443-449 - Florentine Dubois, Valerio Catalano, Marcello Coppola, Frédéric Pétrot:
Accurate on-chip router area modeling with Kriging methodology. 450-457 - Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen:
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. 458-465 - Yinghai Lu, Hai Zhou:
Efficient design space exploration for component-based system design. 466-472 - Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Multiple tunable constant multiplications: Algorithms and applications. 473-479 - Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. 480-487 - Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong:
Memory partitioning and scheduling co-optimization in behavioral synthesis. 488-495 - Andreas C. Cangellaris:
Confronting and exploiting operating environment uncertainty in predictive analysis of signal integrity. 496 - Weng Cho Chew:
Multi-scale, multi-physics analysis for device, chip, package, and board level. 497 - Vikram Jandhyala, Arun V. Sathanur:
Design strategies for high-dimensional electromagnetic systems. 498 - Jin-Fa Lee, Yang Shao, Zhen Peng:
Co-simulations of electromagnetic and thermal effects in electronic circuits using non-conformal numerical methods. 499 - Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian:
ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. 500-507 - Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
Fine-grained hardware/software methodology for process migration in MPSoCs. 508-515 - Xiang Chen, Beiye Liu, Yiran Chen, Mengying Zhao, Chun Jason Xue, Xiaojun Guo:
Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays. 516-522 - Koen Lampaert:
Implementing high-performance, low-power embedded processors: Challenges and solutions: Designer track. 523 - Chien-Ping Lu, Brian Ko:
Latency tolerance for Throughput Computing: Designer track. 524-525 - Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen:
Multi-level cell STT-RAM: Is it realistic or just a dream? 526-532 - Sijing Han, Vijay Sirigiri, Daniel G. Saab, Massood Tabib-Azar:
Ultra-low power NEMS FPGA. 533-538 - Young-Joon Lee, Patrick Morrow, Sung Kyu Lim:
Ultra high density logic designs using transistor-level monolithic 3D integration. 539-546 - Chenjie Gu:
Challenges in post-silicon validation of high-speed I/O links. 547-550 - Xin Li:
Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian Model Fusion. 551-552 - Abhijit Chatterjee, Sabyasachi Deyati, Barry John Muldrey, Shyam Kumar Devarakond, Aritra Banerjee:
Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits. 553-556 - Rawan Abdel-Khalek, Valeria Bertacco:
Functional post-silicon diagnosis and debug for networks-on-chip. 557-563 - John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam:
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. 564-568 - Sheng Wei, Kai Li, Farinaz Koushanfar, Miodrag Potkonjak:
Provably complete hardware Trojan detection using test point insertion. 569-576 - Saro Meguerdichian, Miodrag Potkonjak:
Using standardized quantization for multi-party PPUF matching: Foundations and applications. 577-584 - Wei Hu, Jason Oberg, Dejun Mu, Ryan Kastner:
Simultaneous information flow security and circuit redundancy in Boolean gates. 585-590 - Yuxi Liu, Rong Ye, Feng Yuan, Rakesh Kumar, Qiang Xu:
On logic synthesis for timing speculation. 591-596 - Wenlong Yang, Lingli Wang, Alan Mishchenko:
Lazy man's logic synthesis. 597-604 - Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula:
Minimizing area and power of sequential CMOS circuits using threshold decomposition. 605-612 - Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu:
Performance-driven analog placement considering monotonic current paths. 613-619 - Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu:
Configurable analog routing methodology via technology and design constraint unification. 620-626 - Xin Li, Wangyang Zhang, Fa Wang, Shupeng Sun, Chenjie Gu:
Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion. 627-634 - Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang:
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. 635-642 - Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif:
2012 TAU power grid simulation contest: Benchmark suite and results. 643-646 - Ting Yu, Martin D. F. Wong:
PGT_SOLVER: An efficient solver for power grid transient analysis. 647-652 - Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush : Efficient transient simulation for power grid analysis. 653-659 - Xuanxing Xiong, Jia Wang:
Parallel forward and back substitution for efficient power grid simulation. 660-663 - Peng Li:
Design analysis of IC power delivery. 664-666 - Eli Chiprout:
Power grid effects and their impact on-die. 667-669 - Farid N. Najm:
Overview of vectorless/early power grid verification. 670-677 - Xiaojun Guo, Guangyu Yao, Xiaoli Xu, Wenjiang Liu, Tao Liu:
Transistor technologies and pixel circuit design for efficient active-matrix organic light-emitting diode displays. 678 - Donghwa Shin, Kitae Kim, Naehyuck Chang, Massoud Pedram:
Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCs. 679-686 - Yiran Chen, Xiang Chen, Mengying Zhao, Chun Jason Xue:
Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan. 687-690 - Jianchao Lu, Xiaomi Mao, Baris Taskin:
Clock mesh synthesis with gated local trees and activity driven register clustering. 691-697 - Jia Wang, Xiaodao Chen, Lin Liu, Shiyan Hu:
Fast approximation for peak power driven voltage partitioning in almost linear time. 698-704 - Johann Knechtel, Igor L. Markov, Jens Lienig, Matthias Thiele:
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration. 705-712 - Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh:
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. 713-719 - Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen:
A thermal and process variation aware MTJ switching model and its applications in soft error analysis. 720-727 - Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky:
Modeling and synthesis of quality-energy optimal approximate adders. 728-735 - Shuo Wang, Jifeng Chen, Mohammad Tehranipoor:
Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluation. 736-741 - Matthew R. Guthaus, Baris Taskin:
High-Performance, Low-Power Resonant Clocking: Embedded tutorial. 742-745
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