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ORCIDJerónimo Castrillón
Jerónimo Castrillón Mazo
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- affiliation: TU Dresden, Germany
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2020 – today
- 2020
[j17]Robin Bläsing
, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jerónimo Castrillón, Stuart S. P. Parkin:
Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade. Proc. IEEE 108(8): 1303-1321 (2020)- [j16]Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón:
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. ACM Trans. Archit. Code Optim. 16(4): 56:1-56:23 (2020) - [j15]Asif Ali Khan, Hauke Mewes, Tobias Grosser, Torsten Hoefler, Jerónimo Castrillón:
Polyhedral Compilation for Racetrack Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3968-3980 (2020) - [j14]Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón:
Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories. ACM Trans. Embed. Comput. Syst. 19(6): 44:1-44:26 (2020) - [c56]Alexander Brauckmann, Andrés Goens, Sebastian Ertel, Jerónimo Castrillón:
Compiler-based graph representations for deep learning models of code. CC 2020: 201-211 - [c55]Christian Menard, Andrés Goens, Marten Lohstroh, Jerónimo Castrillón:
Achieving Determinism in Adaptive AUTOSAR. DATE 2020: 822-827 - [c54]Robert Khasanov, Jerónimo Castrillón:
Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping. DATE 2020: 909-914 - [c53]Asif Ali Khan, Andrés Goens, Fazal Hameed, Jerónimo Castrillón:
Generalized Data Placement Strategies for Racetrack Memories. DATE 2020: 1502-1507 - [c52]Alexander Brauckmann, Andrés Goens, Jerónimo Castrillón:
ComPy-Learn: A toolbox for exploring machine learning representations for compilers. FDL 2020: 1-4 - [c51]Marten Lohstroh, Christian Menard, Alexander Schulz-Rosengarten, Matthew Weber, Jerónimo Castrillón, Edward A. Lee:
A Language for Deterministic Coordination Across Multiple Timelines. FDL 2020: 1-8 - [c50]Robert Wittig, Andrés Goens, Christian Menard, Emil Matús, Gerhard P. Fettweis, Jerónimo Castrillón:
Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach. ICT 2020: 1-5 - [c49]Lars Schütze, Jerónimo Castrillón:
Efficient dispatch of multi-object polymorphic call sites in contextual role-oriented programming languages. MPLR 2020: 52-62 - [i11]Robert Khasanov, Jerónimo Castrillón:
Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping. CoRR abs/2001.08094 (2020) - [i10]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
2010 – 2019
- 2019
- [j13]Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón:
RTSim: A Cycle-Accurate Simulator for Racetrack Memories. IEEE Comput. Archit. Lett. 18(1): 43-46 (2019) - [j12]Gerhard P. Fettweis, Meik Dorpinghaus, Jerónimo Castrillón, Akash Kumar, Christel Baier, Karlheinz Bock, Frank Ellinger, Andreas Fery, Frank H. P. Fitzek, Hermann Härtig, Kambiz Jamshidi, Thomas Kissinger, Wolfgang Lehner, Michael Mertig, Wolfgang E. Nagel, Giang T. Nguyen, Dirk Plettemeier, Michael Schröter, Thorsten Strufe:
Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing. Proc. IEEE 107(1): 204-231 (2019) - [j11]Fazal Hameed, Jerónimo Castrillón:
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2375-2386 (2019) - [c48]Marten Lohstroh, Íñigo Íncer Romeo, Andrés Goens, Patricia Derler, Jerónimo Castrillón, Edward A. Lee, Alberto L. Sangiovanni-Vincentelli:
Reactors: A Deterministic Model for Composable Reactive Systems. CyPhy/WESE 2019: 59-85 - [c47]Tobias Reiher, Alexander Senier, Jerónimo Castrillón, Thorsten Strufe:
RecordFlux: Formal Message Specification and Generation of Verifiable Binary Parsers. FACS 2019: 170-190 - [c46]Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jerónimo Castrillón:
STCLang: state thread composition as a foundation for monadic dataflow parallelism. Haskell@ICFP 2019: 146-161 - [c45]Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón:
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. ISLPED 2019: 1-6 - [c44]Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón:
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads. LCTES 2019: 5-18 - [c43]Andrés Goens, Alexander Brauckmann, Sebastian Ertel, Chris Cummins, Hugh Leather, Jerónimo Castrillón:
A case study on machine learning for synthesizing benchmarks. MAPL@PLDI 2019: 38-46 - [c42]Norman A. Rink, Jerónimo Castrillón:
TeIL: a type-safe imperative tensor intermediate language. ARRAY@PLDI 2019: 57-68 - [c41]Andrés Goens, Christian Menard, Jerónimo Castrillón:
On Compact Mappings for Multicore Systems. SAMOS 2019: 325-335 - [c40]Lars Schütze, Jerónimo Castrillón:
Efficient late binding of dynamic function compositions. SLE 2019: 141-151 - [i9]Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón:
ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. CoRR abs/1903.03597 (2019) - [i8]Sebastian Ertel, Justus Adam, Norman A. Rink, Andrés Goens, Jerónimo Castrillón:
Category-Theoretic Foundations of "STCLang: State Thread Composition as a Foundation for Monadic Dataflow Parallelism". CoRR abs/1906.12098 (2019) - [i7]Tobias Reiher, Alexander Senier, Jerónimo Castrillón, Thorsten Strufe:
RecordFlux: Formal Message Specification and Generation of Verifiable Binary Parsers. CoRR abs/1910.02146 (2019) - [i6]Christian Menard, Andres Goens, Marten Lohstroh, Jerónimo Castrillón:
Achieving Determinism in Adaptive AUTOSAR. CoRR abs/1912.01367 (2019) - [i5]Asif Ali Khan, Andres Goens, Fazal Hameed, Jerónimo Castrillón:
Generalized Data Placement Strategies for Racetrack Memories. CoRR abs/1912.03507 (2019) - 2018
- [j10]Jerónimo Castrillón, Matthias Lieber, Sascha Klüppelholz, Marcus Völp, Nils Asmussen, Uwe Aßmann, Franz Baader, Christel Baier, Gerhard P. Fettweis, Jochen Fröhlich, Andrés Goens, Sebastian Haas, Dirk Habich, Hermann Härtig, Mattis Hasler, Immo Huismann, Tomas Karnagel, Sven Karol, Akash Kumar, Wolfgang Lehner, Linda Leuschner, Siqi Ling, Steffen Märcker, Christian Menard, Johannes Mey, Wolfgang E. Nagel, Benedikt Nöthen, Rafael Peñaloza, Michael Raitza, Jörg Stiller, Annett Ungethüm, Axel Voigt, Sascha Wunderlich:
A Hardware/Software Stack for Heterogeneous Systems. IEEE Trans. Multi Scale Comput. Syst. 4(3): 243-259 (2018) - [j9]Sven Karol, Tobias Nett, Jerónimo Castrillón, Ivo F. Sbalzarini:
A Domain-Specific Language and Editor for Parallel Particle Methods. ACM Trans. Math. Softw. 44(3): 34:1-34:32 (2018) - [j8]Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón:
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1059-1072 (2018) - [c39]Sebastian Ertel, Andrés Goens, Justus Adam, Jerónimo Castrillón:
Compiling for concise code and efficient I/O. CC 2018: 104-115 - [c38]Norman A. Rink, Adilla Susungi, Jerónimo Castrillón, Jörg Stiller, Claude Tadonki:
CFDlang: High-level code generation for high-order methods in fluid dynamics. RWDSL@CGO 2018: 5:1-5:10 - [c37]Adilla Susungi, Norman A. Rink, Albert Cohen, Jerónimo Castrillón, Claude Tadonki:
Meta-programming for cross-domain tensor optimizations. GPCE 2018: 79-92 - [c36]Robert Khasanov, Andrés Goens, Jerónimo Castrillón:
Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap. PARMA-DITAM@HiPEAC 2018: 20-25 - [c35]Andres Goens, Christian Menard, Jerónimo Castrillón:
On the Representation of Mappings to Multicores. MCSoC 2018: 184-191 - [c34]Sebastian Ertel, Justus Adam, Jerónimo Castrillón:
Supporting Fine-grained Dataflow Parallelism in Big Data Systems. PMAM@PPoPP 2018: 41-50 - [c33]Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón:
NVMain Extension for Multi-Level Cache Systems. RAPIDO 2018: 7:1-7:6 - 2017
- [j7]Andrés Goens, Sergio Siccha, Jerónimo Castrillón:
Symmetry in Software Synthesis. ACM Trans. Archit. Code Optim. 14(2): 20:1-20:26 (2017) - [c32]Norman A. Rink, Jerónimo Castrillón:
Extending a Compiler Backend for Complete Memory Error Detection. Automotive - Safety & Security 2017: 61-74 - [c31]Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick:
Multi-grained performance estimation for MPSoC compilers: work-in-progress. CASES 2017: 14:1-14:2 - [c30]Norman A. Rink, Jerónimo Castrillón:
Trading Fault Tolerance for Performance in AN Encoding. Conf. Computing Frontiers 2017: 183-190 - [c29]Fazal Hameed, Jerónimo Castrillón:
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization. DATE 2017: 362-367 - [c28]Adilla Susungi, Norman A. Rink, Jerónimo Castrillón, Immo Huismann, Albert Cohen, Claude Tadonki, Jörg Stiller, Jochen Fröhlich:
Towards compositional and generative tensor optimizations. GPCE 2017: 169-175 - [c27]Johanna Sepúlveda, Vania Marangozova-Martin, Jerónimo Castrillón:
Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems (ALCHEMY): Preface. ICCS 2017: 1071-1072 - [c26]Markus Hähnel, Frehiwot Melak Arega, Waltenegus Dargie, Robert Khasanov, Jerónimo Castrillón:
Application interference analysis: Towards energy-efficient workload management on heterogeneous micro-server architectures. INFOCOM Workshops 2017: 432-437 - [c25]Fazal Hameed, Christian Menard, Jerónimo Castrillón:
Efficient STT-RAM last-level-cache architecture to replace DRAM cache. MEMSYS 2017: 141-151 - [c24]Lars Schütze, Jerónimo Castrillón:
Analyzing State-of-the-Art Role-based Programming Languages. Programming 2017: 9:1-9:6 - [c23]Christian Menard, Jerónimo Castrillón, Matthias Jung, Norbert Wehn:
System simulation with gem5 and SystemC: The keystone for full interoperability. SAMOS 2017: 62-69 - [c22]Andrés Goens, Robert Khasanov, Jerónimo Castrillón, Marcus Hähnel, Till Smejkal, Hermann Härtig:
TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings. SCOPES 2017: 11-20 - [c21]Gerald Hempel, Andrés Goens, Jerónimo Castrillón, Josefine Asmus, Ivo F. Sbalzarini:
Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design Centering. SCOPES 2017: 21-30 - [p3]Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng:
MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign 2017: 917-949 - [i4]Tobias Nett, Sven Karol, Jerónimo Castrillón, Ivo F. Sbalzarini:
A Domain-Specific Language and Editor for Parallel Particle Methods. CoRR abs/1704.00032 (2017) - [i3]Andrés Goens, Sergio Siccha, Jerónimo Castrillón:
Symmetry in Software Synthesis. CoRR abs/1704.06623 (2017) - [i2]Jerónimo Castrillón Mazo, Tei-Wei Kuo, Heike E. Riel, Matthias Lieber:
Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061). Dagstuhl Reports 7(2): 1-22 (2017) - 2016
- [j6]Benjamin Schiller, Clemens Deusser, Jerónimo Castrillón, Thorsten Strufe:
Compile- and run-time approaches for the selection of efficient data structures for dynamic graph analysis. Appl. Netw. Sci. 1: 9 (2016) - [j5]Andres Goens, Jerónimo Castrillón, Maximilian Odendahl, Rainer Leupers:
An optimal allocation of memory buffers for complex multicore platforms. J. Syst. Archit. 66-67: 69-83 (2016) - [j4]Jerónimo Castrillón Mazo, Cristina Silvano:
Guest Editorial: Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES). ACM Trans. Embed. Comput. Syst. 16(1): 2:1-2:2 (2016) - [c20]Sven Karol, Norman A. Rink, Bálint Gyapjas, Jerónimo Castrillón:
Fault tolerance with aspects: a feasibility study. MODULARITY 2016: 66-69 - [c19]Andres Goens, Robert Khasanov, Jerónimo Castrillón, Simon Polstra, Andy D. Pimentel:
Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study. MCSoC 2016: 281-288 - [c18]Christian Menard, Andres Goens, Jerónimo Castrillón:
High-level NoC model for MPSoC compilers. NORCAS 2016: 1-6 - [e1]Cristina Silvano, Walter Stechele, Stephan Wong, Jerónimo Castrillón, Michael Hübner, Amir Hossein Ashouri:
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, Automation And Test In Europe (DATE 2016), Dresden, Germany, March 18th, 2016. CEUR Workshop Proceedings 1643, CEUR-WS.org 2016 [contents] - 2015
- [c17]Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers:
Multi/many-core programming: where are we standing? DATE 2015: 1708-1717 - [c16]Andrés Goens, Jerónimo Castrillón:
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs. IESS 2015: 116-127 - [c15]Norman A. Rink, Dmitrii Kuvaiskii, Jerónimo Castrillón, Christof Fetzer:
Compiling for Resilience: the Performance Gap. PARCO 2015: 721-730 - [c14]Diana Göhringer, Michael Hübner, Jerónimo Castrillón, Cristina Silvano:
ViPES 2015 - Preface. SAMOS 2015: 347 - [c13]Benjamin Schiller, Jerónimo Castrillón, Thorsten Strufe:
Efficient Data Structures for Dynamic Graph Analysis. SITIS 2015: 497-504 - [i1]Markus Vogt, Gerald Hempel, Jerónimo Castrillón, Christian Hochberger:
GCC-Plugin for Automated Accelerator Generation and Integration on Hybrid FPGA-SoCs. CoRR abs/1509.00025 (2015) - 2014
- [c12]Luis Gabriel Murillo, Simon Wawroschek, Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
Automatic detection of concurrency bugs through event ordering constraints. DATE 2014: 1-6 - 2013
- [b1]Jerónimo Castrillón Mazo:
Programming heterogeneous MPSoCs: tool flows to close the software productivity gap. RWTH Aachen University, Springer 2013, ISBN 978-3-319-00674-1, pp. 1-231 - [j3]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. Int. J. Embed. Real Time Commun. Syst. 4(1): 64-84 (2013) - [j2]Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. IEEE Trans. Ind. Informatics 9(1): 527-545 (2013) - [c11]Maximilian Odendahl, Jerónimo Castrillón, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Split-cost communication model for improved MPSoC application mapping. ISSoC 2013: 1-8 - [p2]Rainer Leupers, Weihua Sheng, Jerónimo Castrillón:
Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems 2013: 1215-1257 - 2012
- [c10]Jerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid:
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. DAC 2012: 1266-1271 - [c9]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Application-aware spinlock control using a hardware scheduler in MPSoC platforms. ISSoC 2012: 1-6 - 2011
- [j1]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers:
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. Int. J. Embed. Real Time Commun. Syst. 2(3): 1-20 (2011) - [c8]Jerónimo Castrillón, Weihua Sheng, Rainer Leupers:
Trends in embedded software synthesis. ICSAMOS 2011: 347-354 - 2010
- [c7]Rainer Leupers, Jerónimo Castrillón:
MPSoC programming using the MAPS compiler. ASP-DAC 2010: 897-902 - [c6]Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE 2010: 753-758 - [c5]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. SoC 2010: 163-168 - [p1]Rainer Leupers, Weihua Sheng, Jerónimo Castrillón:
Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems 2010: 639-678
2000 – 2009
- 2009
- [c4]Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20 - [c3]Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid:
Task management in MPSoCs: An ASIP approach. ICCAD 2009: 587-594 - 2008
- [c2]Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda:
MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759 - 2005
- [c1]Jerónimo Castrillón, Jorge A. Peña:
Reinforcement Learning with Kohonen-based State Aggregation for Obstacle Avoidance of a Mobile Robot. CIIC 2005: 146-153
Coauthor Index
Andres Goens
aka: Andrés Goens
aka: Andrés Goens
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