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ORCIDICCAD 2024: Newark Liberty International Airport Marriott, NJ, USA
- Jinjun Xiong, Robert Wille:
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2024, Newark Liberty International Airport Marriott, NJ, USA, October 27-31, 2024. ACM 2024, ISBN 979-8-4007-1077-3
The Dawn of Domain-Specific Hardware System for Autonomous Machines
- Yuhao Zhu
:
Imaging, Computing, and Human Perception: Three Agents to Usher in the Autonomous Machine Computing Era. 1:1-1:8 - Zishen Wan, Yuhang Du, Mohamed Ibrahim, Yang (Katie) Zhao, Tushar Krishna, Arijit Raychowdhury:
Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems. 2:1-2:7 - Jason Jabbour, Vijay Janapa Reddi:
Generative AI Agents in Autonomous Machines: A Safety Perspective. 3:1-3:13 - Shaoshan Liu, Yuhao Zhu, Bo Yu, Jean-Luc Gaudiot, Guangrong Gao:
Dataflow Accelerator Architecture for Autonomous Machine Computing. 4:1-4:7
LLM4HWDesign Contest
- Zhongzhi Yu, Chaojian Li, Yongan Zhang, Mingjie Liu, Nathaniel Ross Pinckney, Wenfei Zhou, Haoyu Yang, Rongjian Liang, Haoxing Ren, Yingyan Celine Lin:
Invited Paper: LLM4HWDesign Contest: Constructing a Comprehensive Dataset for LLM-Assisted Hardware Code Generation with Community Efforts. 5:1-5:5
Exploring Attack Vectors and Resilient Defense Strategies in Microelectronics A Special Session on Hardware Security
- Yizhuo Tan, Chuanqi Xu, Jakub Szefer:
Exploration of Timing and Higher-Energy Attacks on Quantum Random Access Memory. 6:1-6:9 - Matchima Buddhanoy, Biswajit Ray:
Fortifying the NAND Flash Supply Chain with Innovative Security Primitives. 7:1-7:7 - Aritri Saha, Ujjwal Guin:
Optimizing Supply Chain Management using Permissioned Blockchains. 8:1-8:7 - Mahsa Tahghigh, Hassan Salmani:
Detecting Hardware Trojans in Manufactured Chips without Reference: A GMM-Based Approach. 9:1-9:7 - Ferhat Erata, Tinghung Chiu, Anthony Etim, Srilalith Nampally, Tejas Raju, Rajashree Ramu, Ruzica Piskac, Timos Antonopoulos, Wenjie Xiong, Jakub Szefer:
Systematic Use of Random Self-Reducibility in Cryptographic Code against Physical Attacks. 10:1-10:9
Computing over Encrypted Data: Novel Acceleration of Fully Homomorphic Encryption on Hardware Platforms
- Tianyou Bao, Pengzhou He, Jiafeng Xie:
Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach. 11:1-11:9 - Ming-Chien Ho, Yu-Te Ku, Yu Xiao, Feng-Hao Liu, Chih-Fan Hsu, Ming-Ching Chang, Shih-Hao Hung, Wei-Chao Chen:
Invited Paper: Efficient Design of FHEW/TFHE Bootstrapping Implementation with Scalable Parameters. 12:1-12:9 - Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy:
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE. 13:1-13:9 - Antian Wang, Kaiyuan Zhang, Keshab K. Parhi, Yingjie Lao:
HERMES: Homomorphic Encryption over Residual Number System for Multi-level EvaluationS. 14:1-14:7
Advanced Partitioning and Floorplanning
- Magi Chen, Ting-Chi Wang:
A Hypergraph Partitioner Utilizing a Novel Graph Generative Model. 15:1-15:9 - Shunyang Bi, Jing Tang, Hailong You, Haonan Wu, Cong Li, Richard Sun:
TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation. 16:1-16:9 - Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang:
Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. 17:1-17:9 - Xingbo Du, Ruizhe Zhong, Shixiong Kai, Zhentao Tang, Siyuan Xu, Jianye Hao, Mingxuan Yuan, Junchi Yan:
JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whitespace and Overlap among Complex Rectilinear Modules. 18:1-18:9
State-of-the-Art Placement
- Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
Fusion of Global Placement and Gate Sizing with Differentiable Optimization. 19:1-19:9 - Donghao Fang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu:
SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs. 20:1-20:8 - Jai-Ming Lin, Wei-Yuan Lin, Yung-Chen Chen, Pin-Yu Chen, Chen-Fa Tsai, De-Shiun Fu, Che-Li Lin:
An Effective Analytical Placement Approach to Handle Fence Region Constraint. 21:1-21:8 - Bangqi Fu, Lixin Liu, Martin D. F. Wong, Evangeline F. Y. Young:
Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration. 22:1-22:9
TUTORIAL SESSION: Hardware Security Trust and Verification
- Dan Niu, Yiyang Tao, Zhou Jin, Yichao Dong, Chao Wang, Changyin Sun:
ISLU: Indexing-Efficient Sparse LU Factorization for Circuit Simulation on GPUs. 23:1-23:9
Advancing AI: Cross-Disciplinary Insights into Next-Gen Tools, Tech & Architectures
- Sumit Diware, Mohammad Amin Yaldagard, Rajendra Bishnoi:
Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks. 24:1-24:9 - Farshad Firouzi, Sri Sai Rakesh Nakkilla, Chenghao Fu, Sanmitra Banerjee, Jonti Talukdar, Krishnendu Chakrabarty:
LLM-AID: Leveraging Large Language Models for Rapid Domain-Specific Accelerator Development. 25:1-25:9 - Anup Das:
Neuromorphic Computing for Graph Analytics. 26:1-26:7 - Mahdi Nikdast, Salma Afifi, Sudeep Pasricha:
Shedding Light on LLMs: Harnessing Photonic Neural Networks for Accelerating LLMs. 27:1-27:8
AI4HLS: New Frontiers in High-Level Synthesis Augmented with Artificial Intelligence
- Nicolas Bohm Agostini, Giovanni Gozzi, Michele Fiorito, Claudio Barone, Serena Curzel, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Fabrizio Ferrandi, Antonino Tumeo:
Extending High-Level Synthesis with AI/ML Methods. 28:1-28:6 - Yuchao Liao, Tosiron Adegbija, Roman Lysecky:
Are LLMs Any Good for High-Level Synthesis? 29:1-29:8
EDA for Quantum
- Enhyeok Jang, Seungwoo Choi, Youngmin Kim, Jeewoo Seo, Won Woo Ro:
Barber: Balancing Thermal Relaxation Deviations of NISQ Programs by Exploiting Bit-Inverted Circuits. 30:1-30:9 - Hanyu Wang, Daniel Bochen Tan, Jason Cong:
Quantum State Preparation Circuit Optimization Exploiting Don't Cares. 31:1-31:9 - Nicholas S. DiBrita, Daniel Leeds, Yuqian Huo, Jason Ludmir, Tirthak Patel:
ReCon: Reconfiguring Analog Rydberg Atom Quantum Computers for Quantum Generative Adversarial Networks. 32:1-32:9 - Sheng-Tan Huang, Ying-Jie Jiang, Shao-Yun Fang, Chung-Kuan Cheng:
SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture. 33:1-33:8
Techniques foR Reliability Modeling and Analysis
- Yue Qian, Lan Chen:
A Neural-Ordinary-Differential-Equations Based Generic Approach for Process Modeling in DTCO: A Case Study in Chemical-Mechanical Planarization and Copper Plating. 34:1-34:9 - Yuqi Jiang, Xudong Lu, Qian Jin, Qi Sun, Hanming Wu, Cheng Zhuo:
FabGPT: An Efficient Large Multimodal Model for Complex Wafer Defect Knowledge Queries. 35:1-35:8 - Yanfang Liu, Lei He, Wei W. Xing:
Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis. 36:1-36:9 - Subed Lamichhane, Mohammadamir Kavousi, Sheldon X.-D. Tan:
BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural Networks. 37:1-37:9
Layout and Cell Optimization
- Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim:
Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. 38:1-38:8 - Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang:
ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. 39:1-39:9 - Aditya Sridharan Iyer, Daehyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim:
Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line Folding. 40:1-40:9 - Jiun-Cheng Tsai, Wei-Min Hsu, Yun-Ting Hsieh, Yu-Ju Li, Wei Huang, C. N. Ho, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Aaron C.-W. Liang, Charles H.-P. Wen:
MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint Learning. 41:1-41:9
Quantum Simulation and Quantum Cloud
- Tian-Fu Chen, Yu-Fang Chen, Jie-Hong Roland Jiang, Sára Jobranová, Ondrej Lengál:
Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization. 42:1-42:9 - Jindi Wu, Tianjie Hu, Qun Li:
Detecting Fraudulent Services on Quantum Cloud Platforms via Dynamic Fingerprinting. 43:1-43:8 - Wenjie Wu, Yiquan Wang, Ge Yan, Yuming Zhao, Bo Zhang, Junchi Yan:
On Reducing the Execution Latency of Superconducting Quantum Processors via Quantum Job Scheduling. 44:1-44:9 - Xiangyu Ren, Mengyu Zhang, Antonio Barbalace:
A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit Knitting. 45:1-45:9
Optimizations in Lithography and Physical Design
- Yang Luo, Xiaoxiao Liang, Yuzhe Ma:
Enabling Robust Inverse Lithography with Rigorous Multi-Objective Optimization. 46:1-46:9 - Guojin Chen, Haoyu Yang, Haoxing Mark Ren, Bei Yu, David Z. Pan:
Differentiable Edge-based OPC. 47:1-47:9 - Guohao Chen, Chang Liu, Xingyu Tong, Peng Zou, Jianli Chen:
A Co-optimization Framework with Multi-layer Constraints for Manufacturability. 48:1-48:9 - Jing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang:
MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management. 49:1-49:9
When Diverse Architectures Meet Diverse Ais
- Ruiyang Qin, Zheyu Yan, Dewen Zeng, Zhenge Jia, Dancheng Liu, Jianbo Liu, Ahmed Abbasi, Zhi Zheng, Ningyuan Cao, Kai Ni, Jinjun Xiong, Yiyu Shi:
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures. 50:1-50:9 - Shuzhang Zhong, Ling Liang, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li:
AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. 51:1-51:9 - Zebin Yang, Renze Chen, Taiqiang Wu, Ngai Wong, Yun Liang, Runsheng Wang, Ru Huang, Meng Li:
MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers. 52:1-52:9 - Yifan Qin, Zheyu Yan, Zixuan Pan, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi:
TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators. 53:1-53:9
TUTORIAL SESSION: Heterogeneous Integration: From Physical Layer to Architecture and Packaging
- Adrian Evans, César Fuguet, Davy Million:
OpenSource Heterogeneous Chiplet-based Computing Architectures. 54:1-54:8 - Chukwufumnanya Ogbogu, Gaurav Narang, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande:
Heterogeneous Manycore In-Memory Computing Architectures. 55:1-55:7 - Christopher Bailey, Leslie Hwang, Fnu Pallavi Praful:
Package Modeling and Analysis for Heterogeneous Integration. 56:1-56:7
Towards Democratized and Reproducible AI for EDA Research: Open Datasets and Benchmarks in Various Aspects
- Vidya A. Chhabria, Bing-Yue Wu, Utsav Sharma, Kishor Kunal, Austin Rovinski, Sachin S. Sapatnekar:
Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants. 57:1-57:7 - Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Yiran Chen, Hai Helen Li:
EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. 58:1-58:8 - Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. 59:1-59:9 - Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie:
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. 60:1-60:9
Exploring Quantum Technologies in Practical Applications
- Yuchen Zhu, Yidong Zhou, Jinglei Cheng, Yuwei Jin, Boxi Li, Siyuan Niu, Zhiding Liang:
Compiler Optimizations for QAOA. 61:1-61:7 - Atefeh Sohrabizadeh, Wan-Hsuan Lin, Daniel Bochen Tan, Madelyn Cain, Sheng-Tao Wang, Mikhail D. Lukin, Jason Cong:
GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set. 62:1-62:6 - Zichang He, Ruslan Shaydulin, Dylan Herman, Changhao Li, Rudy Raymond, Shree Hari Sureshbabu, Marco Pistoia:
Parameter Setting Heuristics Make the Quantum Approximate Optimization Algorithm Suitable for the Early Fault-Tolerant Era. 63:1-63:7 - Yiwen Liu, Qingyue Jiao, Yiyu Shi, Ke Wan, Shangjie Guo:
A comparison on constrain encoding methods for quantum approximate optimization algorithm. 64:1-64:7
Timing Prediction and Acceleration
- Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang:
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. 65:1-65:9 - Linyu Zhu, Yichen Cai, Xinfei Guo:
One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff. 66:1-66:9 - Sanjay Gandham, Joe Walston, Sourav Samanta, Lingxiang Yin, Hao Zheng, Mingjie Lin, Stelios Diamantidis:
CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation. 67:1-67:9 - Zhengyang Lyu, Xiaqing Li, Zidong Du, Qi Guo:
Explainable and Layout-Aware Timing Prediction. 68:1-68:9
How Much ML Can You Squeeze into Your Edge Device?
- Zhenyu Wang, Ao Ren, Duo Liu, Haining Fang, Jiaxing Shi, Yujuan Tan, Xianzhang Chen:
RACI: A Resource-Aware Cooperative Inference Framework on Heterogeneous Edge Devices. 69:1-69:9 - Ziyu Ying, Sandeepa Bhuyan, Yingtian Zhang, Yan Kang, Mahmut T. Kandemir, Chita R. Das:
Foveated HDR: Efficient HDR Content Generation on Edge Devices Leveraging User's Visual Attention. 70:1-70:9 - Soyed Tuhin Ahmed, Michael Hefenbrock, Mehdi B. Tahoori:
Tiny Deep Ensemble: Uncertainty Estimation in Edge AI Accelerators via Ensembling Normalization Layers with Shared Weights. 71:1-71:9 - Shiwei Liu, Guanchen Tao, Yifei Zou, Derek Chow, Zichen Fan, Kauna Lei, Bangfei Pan, Dennis Sylvester, Gregory Kielian, Mehdi Saligane:
ConSmax: Hardware-Friendly Alternative Softmax with Learnable Parameters. 72:1-72:9
Reliable Emerging Technologies
- Dennis Rich, Tathagata Srimani, Mohamadali Malakoutian, Srabanti Chowdhury, Subhasish Mitra:
Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal Scaffolding. 73:1-73:9 - Earl Kim, Hyunuk Cho, Sungjun Cho, Myungsuk Kim, Jisung Park, Jaeyong Jeong, Eunkyoung Kim, Sunghoi Hur:
NORNS: Three Guides for Efficient Automatic Post-Fabrication Optimization of Modern NAND Flash Memory. 74:1-74:9 - Liaoyuan Cheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation. 75:1-75:8 - Taixin Li, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Kai Ni, Huazhong Yang, Thomas Kämpfe, Xueqing Li:
REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control. 76:1-76:9
Innovative Approaches in Circuit Simulation: High-Fidelity Modeling: Optimization: and Parallelization
- Shao-Yu Lo, MaoZe Liu, Yao-Wen Chang:
Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging Analysis. 77:1-77:9 - Jiatai Sun, Xiaru Zha, Chao Wang, Xiao Wu, Dan Niu, Wei W. Xing, Zhou Jin:
Pseudo Adjoint Optimization: Harnessing the Solution Curve for SPICE Acceleration. 78:1-78:9 - Yuxuan Zhao, Xiaoyu Yang, Yinuo Bai, Lijie Zeng, Dan Niu, Weifeng Liu, Zhou Jin:
CSP: Comprehensively-Sparsified Preconditioner for Efficient Nonlinear Circuit Simulation. 79:1-79:9 - Hang Zhou, Quan Chen:
EI-PIT: A Parallel-in-Time Exponential Integrator Method for Transient Linear Circuit Simulation. 80:1-80:8
Analog: Analog: and More Analog Design using Your Favorite AI Algorithms
- Yuxuan Yin, Yu Wang, Boxun Xu, Peng Li:
ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models. 81:1-81:9 - Jinglin Han, Yuhao Leng, Xiuli Zhang, Peng Wang:
TSO-Flow: A Topology Synthesis and Optimization Workflow for Operational Amplifiers with Invertible Graph Generative Model. 82:1-82:9 - Zhengqi Gao, Fan-Keng Sun, Ron Rohrer, Duane S. Boning:
KirchhoffNet: A Scalable Ultra Fast Analog Neural Network. 83:1-83:9 - Xiaoman Yang, Hai-Bao Chen, Wenjie Zhu, Yuhan Zhang, Yongkang Xue, Pengpeng Ren, Runsheng Wang, Zhigang Ji, Ru Huang:
Enforcing hard constraints in physics-informed learning for transient TSV electromigration analysis. 84:1-84:9
Emerging Technologies Enabling Content Addressable Memories
- Yifei Zhou, Thomas Kämpfe, Kai Ni, Hussam Amrouch, Cheng Zhuo, Xunzhao Yin:
TReCiM: Lower Power and Temperature-Resilient Multibit 2FeFET-1T Compute-in-Memory Design. 85:1-85:9 - John Moon, Giacomo Pedretti, Pedro Bruel, Sergey Serebryakov, Omar Eldash, Luca Buonanno, Catherine E. Graves, Paolo Faraboschi, Jim Ignowski:
CAMSHAP: Accelerating Machine Learning Model Explainability with Analog CAM. 86:1-86:9 - Peiyi He, Ruibin Mao, Keyi Shan, Yunwei Tong, Zhicheng Xu, Muyuan Peng, Ruibang Luo, Can Li:
ShiftCAM: A Time-Domain Content Addressable Memory Utilizing Shifted Hamming Distance for Robust Genome Analysis. 87:1-87:9 - Chenyu Ni, Sijie Chen, Che-Kai Liu, Liu Liu, Mohsen Imani, Thomas Kämpfe, Kai Ni, Michael T. Niemier, Xiaobo Sharon Hu, Cheng Zhuo, Xunzhao Yin:
TAP-CAM: A Tunable Approximate Matching Engine based on Ferroelectric Content Addressable Memory. 88:1-88:9
Processor: Memory: And Storage Designs
- Saeideh Sheikhpour, David Metz, Erling Jellum, Magnus Själander, Lieven Eeckhout:
Sustainable High-Performance Instruction Selection for Superscalar Processors. 89:1-89:9 - Mohamed Abuelala, Mohamed Hassan:
A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads. 90:1-90:9 - Yingjia Wang, Lok Yin Chow, Xirui Nie, Yuhong Liang, Ming-Chang Yang:
ZnH2: Augmenting ZNS-based Storage System with Host-Managed Heterogeneous Zones. 91:1-91:8
Innovating Data Storage: Exploring Adaptive Indexing: Access Pattern Optimization: and Memory Longevity Enhancement for SSDs
- Che-Wei Lin, Chun-Feng Wu:
ALISA: An Adaptive Learned Index Structure for Spatial Data on Solid-State Drives. 92:1-92:9 - Qian Wei, Xiaosu Guo, Jie Wang, Zhaoyan Shen, Dongxiao Yu, Zhiping Jia, Bingzhe Li:
An Access Pattern-aware Hybrid Learning-based and Conventional Mapping for Solid-State Drives. 93:1-93:9 - Han-Yu Liao, Yi-Shen Chen, Jen-Wei Hsieh, Hung-Pin Chen, Yuan-Hao Chang:
CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming. 94:1-94:9
Enhancing Simulation Efficiency through Multi-Core/GPU-Acceleration and Instruction-Level Fault Injection
- Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li:
DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. 95:1-95:9 - Yanqing Zhang, Haoxing Ren, Brucek Khailany:
GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method. 96:1-96:9 - Yi Yuan, Derek Chiou:
Accelerating Fault Injection for Validating Processor RTL Implementations. 97:1-97:9
Let LLMs Generate Your RTL Code!
- Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu:
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. 98:1-98:7 - Fan Cui, Chenyang Yin, Kexing Zhou, Youwei Xiao, Guangyu Sun, Qiang Xu, Qipeng Guo, Yun Liang, Xingcheng Zhang, Demin Song, Dahua Lin:
OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection. 99:1-99:9 - Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang:
MEIC: Re-thinking RTL Debug Automation using LLMs. 100:1-100:9
Architectural Mapping
- Yue Liang, Di Mou, Dajiang Liu:
DISC: Exploiting Data Parallelism of Non-Stencil Computations on CGRAs via Dynamic Iteration Scheduling. 101:1-101:9 - Mingzhe Zhang, Xiaochen Hao, Hongbo Rong, Wenguang Chen:
MatFactory: A Framework for High-Performance Matrix Factorization on FPGAs. 102:1-102:9 - Shengbo Tong, Haoyuan Li, Jiahao Xu, Chunyan Pei, Wenjian Yu, Shengjun Liu, Jian Shen:
EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation. 103:1-103:9
IR Drop and High-Speed Link Analysis
- Yihan Wen, Juan Li, Bei Yu, Xiaoyi Wang:
Peak Power and Dynamic IR-drop Assessment via Waveform Augmenting. 104:1-104:9 - Yu-Tung Liu, Yu-Hao Cheng, Shao-Yu Wu, Hung-Ming Chen:
CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Network. 105:1-105:9 - Songyu Sun, Xiao Dong, Yanliang Sha, Quan Chen, Cheng Zhuo:
LiTformer: Efficient Modeling and Analysis of High-Speed Link Transmitters Using Non-Autoregressive Transformer. 106:1-106:9
Efficient Machine Learning: From Cloud to Edge
- Yongbo Yu, Fuxun Yu, Zhi Tian, Xiang Chen:
GACER: Granularity-Aware ConcurrEncy Regulation for Multi-Tenant Deep Learning. 107:1-107:9 - Andreas Karatzas, Iraklis Anagnostopoulos:
MapFormer: Attention-based multi-DNN manager for throughout & power co-optimization on embedded devices. 108:1-108:9 - Jun Xia, Yi Zhang, Yiyu Shi:
Towards Energy-Aware Federated Learning via MARL: A Dual-Selection Approach for Model and Client. 109:1-109:9
EdgeML: Efficient and Private ML for the Edge
- Tong Zhou, Jiahui Zhao, Yukui Luo, Xi Xie, Wujie Wen, Caiwen Ding, Xiaolin Xu:
AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing. 110:1-110:9 - Yi Xiong, Weihong Liu, Rui Zhang, Yulong Zu, Zongwei Zhu, Xuehai Zhou:
EPipe: Pipeline Inference Framework with High-quality Offline Parallelism Planning for Heterogeneous Edge Devices. 111:1-111:10 - Hanqiu Chen, Xuebin Yao, Pradeep Subedi, Cong Hao:
Residual-INR: Communication Efficient On-Device Learning Using Implicit Neural Representation. 112:1-112:9
Advances in Verification through SAT Solving and Machine Learning
- Sven Thijssen, Muhammad Rashedul Haq Rashed, Md Rubel Ahmed, Suraj Singireddy, Sumit Kumar Jha, Rickard Ewetz:
Equivalence Checking for Flow-Based Computing using Iterative SAT Solving. 113:1-113:9 - Yu Zhang, Hui-Ling Zhen, Mingxuan Yuan, Bei Yu:
DiffSAT: Differential MaxSAT Layer for SAT Solving. 114:1-114:7 - Zhiyuan Yan, Hongce Zhang:
Word-Level Augmentation of Formal Proof by Learning from Simulation Traces. 115:1-115:9
New Benchmarks and Understanding Benchmarks using LLMs
- Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. 116:1-116:9 - Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang:
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. 117:1-117:9 - Uday Mallappa, Hesham Mostafa, Mikhail Galkin, Mariano Phielipp, Somdeb Majumdar:
FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SOCs. 118:1-118:9
Applications and Architectures
- Hassan Nassar, Philipp Machauer, Lars Bauer, Dennis Gnad, Mehdi Baradaran Tahoori, Jörg Henkel:
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering. 119:1-119:9 - Qingyu Guo, Jiayong Wan, Songqiang Xu, Meng Li, Yuan Wang:
HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline. 120:1-120:9 - Pranav Dangi, Thilini Kaushalya Bandara, Saeideh Sheikhpour, Tulika Mitra, Lieven Eeckhout:
Sustainable Hardware Specialization. 121:1-121:9
Machine Learning-Based Design and Timing Optimization
- Peng Xu, Su Zheng, Yuyang Ye, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu:
RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization. 122:1-122:7 - Zhanhua Zhang, Wenjie Ding, Guoqing He, Peng Cao:
LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion. 123:1-123:9 - Wenjie Ding, Zhanhua Zhang, Guoqing He, Peng Cao:
A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural Network. 124:1-124:9
Co-Designing NVM-Based Systems for Machine Learning Applications
- Jörg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei:
Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications. 125:1-125:8 - Xiaoyu Sun, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar:
Non-volatile Memory Technologies for Edge AI Applications. 126:1-126:7
Delocalizing AI with Emerging Edge Intelligence (IoT/Internet)
- Mahdi Morafah, Hojin Chang, Bill Lin:
Large Scale Delocalized Federated Learning Over a Huge Diversity of Devices in Emerging Next-Generation Edge Intelligence Environments. 127:1-127:8 - Anxiao Jiang:
Error Correction and Detection for Analog AI Computing in Edge Systems. 128:1-128:7 - Dharanidhar Dang, Priyabrata Dash, Luqi Zheng, Haitong Li:
Co-designing 2.5D Silicon Photonic Accelerators for Distributed Transformer at the Edge. 129:1-129:9 - Shaloo Rakheja:
A materials- and devices-centric approach to neuromorphic computing. 130:1-130:9 - Akul Malhotra, Sumeet Kumar Gupta:
Fault Tolerant In-Memory Computing based on Emerging Technologies for Ultra-Low Precision Edge AI Accelerators. 131:1-131:9
Let AI Power Your Synthesis and Defect Analysis!
- Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
The Power of Graph Signal Processing for Chip Placement Acceleration. 132:1-132:8 - Zijian Ding, Atefeh Sohrabizadeh, Weikai Li, Zongyue Qin, Yizhou Sun, Jason Cong:
Efficient Task Transfer for HLS DSE. 133:1-133:9 - Qian Jin, Yuqi Jiang, Xudong Lu, Yumeng Liu, Yining Chen, Dawei Gao, Qi Sun, Cheng Zhuo:
SEM-CLIP: Precise Few-Shot Learning for Nanoscale Defect Detection in Scanning Electron Microscope Image. 134:1-134:8
Revolutionizing AI with Low Power Accelerators: Emerging Design Trends
- Likai Pei, Yifan Qin, Zephan M. Enciso, Boyang Cheng, Jianbo Liu, Steven Davis, Zhenge Jia, Michael T. Niemier, Yiyu Shi, Xiaobo Sharon Hu, Ningyuan Cao:
Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks. 135:1-135:9 - Yixuan Hu, Yikang Jia, Meng Li, Yuan Wang, Runsheng Wang, Ru Huang:
OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation. 136:1-136:9 - Vojtech Mrazek, Argyris Kokkinis, Panagiotis Papanikolaou, Zdenek Vasícek, Kostas Siozios, Georgios Tzimpragos, Mehdi B. Tahoori, Georgios Zervakis:
Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks. 137:1-137:9
New Techniques in Analog Optimization: Bayesian Sensitivity: Hierarchical Placement: and AI-Driven 2.5D Chiplet Design
- Ruiyu Lyu, Aidong Zhao, Yuan Meng, Keren Zhu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng:
Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. 138:1-138:9 - Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang:
Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. 139:1-139:9 - Seungmin Woo, Pruek Vanna-Iampikul, Sung Kyu Lim:
AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design Quality. 140:1-140:9
Dive into the Design Space for Design Automation
- Yuanhang Gao, Donger Luo, Chen Bai, Bei Yu, Hao Geng, Qi Sun, Cheng Zhuo:
Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization? 141:1-141:9 - Yang Liu, Tianchen Wang, Yuxuan Dong, Zexu Zhang, Shun Li, Jun Yu, Kun Wang:
TransLib: An Extensible Graph-Aware Library Framework for Automated Generation of Transformer Operators on FPGA. 142:1-142:9 - Mingju Liu, Daniel Robinson, Yingjie Li, Cunxi Yu:
MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning. 143:1-143:10
Machine Learning Innovations for Thermal and Power Optimization
- Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang:
FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects. 144:1-144:9 - Yanchi Dong, Xueping Liu, Xiaochen Hao, Yun Liang, Ru Huang, Le Ye, Tianyu Jia:
Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. 145:1-145:9 - Mingyue Wang, Yuanqing Cheng, Weiheng Zeng, Zhenjie Lu, Vasilis F. Pavlidis, Wei Xing:
ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis With Active Learning. 146:1-146:9
Routing and ECO Routing
- Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin:
HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method. 147:1-147:9 - Shiju Lin, Liang Xiao, Jinwei Liu, Evangeline F. Y. Young:
InstantGR: Scalable GPU Parallelization for Global Routing. 148:1-148:8 - Che-Ping Tsai, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang:
An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. 149:1-149:9
Application Specific Accelerations
- Jinhao Li, Jiaming Xu, Shiyao Li, Shan Huang, Jun Liu, Yaoxiu Lian, Guohao Dai:
Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous Dequantization. 150:1-150:9 - Lei Dai, Ziming Yuan, Wen Li, Shengwen Liang, Kaiwei Zou, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. 151:1-151:9 - Zehua Li, Kaisheng Ma:
Partial Differential Equation Acceleration by Exploiting Value Similarity. 152:1-152:9
Enabling Sustainable Next Generation IoT and CPS
- Yanjun Zhang, Xiaoyu Niu, Yifan Zhang, Hongzheng Tian, Bo Yu, Shaoshan Liu, Sitao Huang:
A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design. 153:1-153:9 - Fatemeh Asgarinejad, Flavio Ponzina, Onat Güngör, Tajana Rosing, Baris Aksanli:
HDXpose: Harnessing Hyperdimensional Computing's Explainability for Adversarial Attacks. 154:1-154:9 - Gan Fang, Jongouk Choi, Changhee Jung:
Hybrid Power Failure Recovery for Intermittent Computing. 1-9
Cycle-Accurate Timing Models: RISC-V Test Failure Analysis: and Low-Power Design Verification
- Yu Zeng, Aarti Gupta, Sharad Malik:
Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware Accelerators. 155:1-155:8 - Manfred Schlägl, Daniel Große:
Single Instruction Isolation for RISC-V Vector Test Failures. 156:1-156:9 - Yu-An Shih, Sharad Malik:
Automatic Verification and Identification of Partial Retention Register Sets for Low-Power Designs. 157:1-157:9
Bayesian Techniques for Software-Hardware Co-Optimization and Routing
- Chien-Yi Yang, Minxuan Zhou, Flavio Ponzina, Suraj Sathya Prakash, Raid Ayoub, Pietro Mercati, Mahesh Subedar, Tajana Rosing:
Multi-Objective Software-Hardware Co-Optimization for HD-PIM via Noise-Aware Bayesian Optimization. 158:1-158:9 - Siyuan Liang, Rongliang Fu, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. 159:1-159:9 - Hamza Errahmouni Barkam, Tamoghno Das, Prathyush Poduval, Sungjeon Jeong, Calvin Yeung, Mostafa A. Solitan, Mohsen Imani:
Bayesian-Informed Hyperdimensional Learning for Intelligent and Efficient Data Processing. 160:1-160:9
Design Frameworks and Post-Place Optimization
- Kyounghun Kang, Wanyeong Jung:
SeGen: Automatic Topology Generator for Sequencing Elements. 161:1-161:9 - Jaemin Seo, Sejin Park, Seokhyeong Kang:
Improving Timing & Power Trade-off in Post-place Optimization Using Multi-agent Reinforcement Learning. 162:1-162:9
Advances in Analog and RF Synthesis: Machine Learning Techniques and Thermal Analysis
- Hyunsu Chae, Hao Yu, Sensen Li, David Z. Pan:
PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design. 163:1-163:9 - Ali Hammoud, Anhang Li, Wen Tian, Ayushman Tripathi, Harsh Khandeparkar, Ryan Wans, Gregory Kielian, Boris Murmann, Dennis Sylvester, Mehdi Saligane:
Reinforcement Learning-Enhanced Cloud-Based Open Source Analog Circuit Generator for Standard and Cryogenic Temperatures in 130-nm and 180-nm OpenPDKs. 164:1-164:7 - Nibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar:
Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers. 165:1-165:9
Microarchitecture Support for Security
- Saion K. Roy, Naresh R. Shanbhag:
On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks. 166:1-166:9 - Zhaojun Lu, Peng Xu, Yijie Wang, Yifan Yang, Qidong Chen, Weizong Yu, Gang Qu:
An FPGA-based Key-Switching Accelerator with Ultra-High Throughput for FHE. 167:1-167:9 - Upasana Mandal, Shubhi Shukla, Ayushi Rastogi, Sarani Bhattacharya, Debdeep Mukhopadhyay:
µLAM: A LLM-Powered Assistant for Real-Time Micro-architectural Attack Detection and Mitigation. 168:1-168:9
New Research Developments in Synthesis
- Chandrabhusan Reddy Chigarapally, Harshwardhan Nitin Bhakkad, Animesh Basak Chowdhury, Chandan Karfa, Sukanta Bhattacharjee:
LEAP: Learning guided Quality Cut selection for faster Technology Mapping. 169:1-169:6 - Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo:
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. 170:1-170:11 - Hongyang Pan, Cunqing Lan, Yiting Liu, Zhiang Wang, Li Shang, Xuan Zeng, Fan Yang, Keren Zhu:
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. 171:1-171:9
CTS and FPGA Routing
- Aristotelis Tsekouras, Georgios Kyriazidis, Gage Hills, Vasilis Pavlidis:
OCTS: An Optical Clock Tree Synthesis Methodology for 2.5D Systems. 172:1-172:9 - Xinming Wei, Ziyun Zhang, Sunan Zou, Kaiwen Sun, Jiahao Zhang, Jiaxi Zhang, Ping Fan, Guojie Luo:
AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration. 173:1-173:9 - Xinshi Zang, Wenhao Lin, Jinwei Liu, Evangeline F. Y. Young:
Potter: A Parallel Overlap-Tolerant Router for UltraScale FPGAs. 174:1-174:8
PIM PIM PIM
- Hongtao Zhong, Taixin Li, Yiming Chen, Wenjun Tang, Juejian Wu, Huazhong Yang, Xueqing Li:
NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data. 175:1-175:9 - Hoon Shin, Rihae Park, Jae W. Lee:
A Processing-using-Memory Architecture for Commodity DRAM Devices with Enhanced Compatibility and Reliability. 176:1-176:10 - Lidong Guo, Zhenhua Zhu, Tengxuan Liu, Xuefei Ning, Shiyao Li, Guohao Dai, Huazhong Yang, Wangyang Fu, Yu Wang:
Towards Floating Point-Based Attention-Free LLM: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications. 177:1-177:9
Real-Time AI: Co-Designing for the Edge
- Chao Wu, Yifan Gong, Liangkai Liu, Mengquan Li, Yushu Wu, Xuan Shen, Zhimin Li, Geng Yuan, Weisong Shi, Yanzhi Wang:
AyE-Edge: Automated Deployment Space Search Empowering Accuracy yet Efficient Real-Time Object Detection on the Edge. 178:1-178:9 - Shuai Zhou, Sisi Meng, Huinan Tian, Jun Yu, Kun Wang:
Edge-BiT: Software-Hardware Co-design for Optimizing Binarized Transformer Networks Inference on Edge FPGA. 179:1-179:9 - Yuhao Ji, Chao Fang, Shaobo Ma, Haikuo Shao, Zhongfeng Wang:
Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment. 180:1-180:9
Security by Design and Pre-Silicon Security Assurance
- Flavien Solt, Kaveh Razavi:
HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware. 181:1-181:9 - Anna Lena Duque Antón, Johannes Müller, Philipp Schmitz, Tobias Jauch, Alex Wezel, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL. 182:1-182:9 - Melisande Zonta-Roudes, Andres Meza, Nora Hinderling, Lucas Deutschmann, Francesco Restuccia, Ryan Kastner, Shweta Shinde:
eXpect: On the Security Implications of Violations in AXI Implementations. 183:1-183:9
A New Life to Logic Synthesis
- Zhengyuan Shi, Ziyang Zheng, Sadaf Khan, Jianyuan Zhong, Min Li, Qiang Xu:
DeepGate3: Towards Scalable Circuit Representation Learning. 184:1-184:9 - Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi:
PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network. 185:1-185:9 - Chang Meng, Mingfei Yu, Hanyu Wang, Wayne P. Burleson, Giovanni De Micheli:
RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats. 186:1-186:9
Machine Learning for P&R and Post-P&R
- Bugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R. Guthaus:
GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs. 187:1-187:7 - Andrew B. Kahng, Sayak Kundu, Dooseok Yoon:
Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation. 188:1-188:9 - Jinoh Cho, Seonghyeon Park, Jakang Lee, Sung-Yun Lee, Jinmo Ahn, Seokhyeong Kang:
RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning. 189:1-189:8
Bringing Device Flavours
- Yilmaz Ege Gonul, Baris Taskin:
Multi-phase Coupled CMOS Ring Oscillator based Potts Machine. 190:1-190:9 - S. M. Mojahidul Ahsan, Muhammad Sakib Shahriar, Mrittika Chowdhury, Tanvir Hossain, Md Sakib Hasan, Tamzidul Hoque:
Accurate, Yet Scalable: A SPICE-based Design and Optimization Framework for eNVM based Analog In-memory Computing. 191:1-191:9
IP: Side-Channels: and Acceleration
- Kwunhang Wong, Songqi Wang, Wei Huang, Xinyuan Zhang, Yangu He, Karl Ming Him Lai, Yuzhong Jiao, Ning Lin, Xiaojuan Qi, Xiaoming Chen, Zhongrui Wang:
SNNGX: Securing Spiking Neural Networks with Genetic XOR Encryption on RRAM-based Neuromorphic Accelerator. 192:1-192:9 - Jitendra Bhandari, Animesh Basak Chowdhury, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel:
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. 193:1-193:8 - Anees Ahmed, Nojan Sheybani, Davi Moreno, Nges Brian Njungle, Tengkai Gong, Michel A. Kinsy, Farinaz Koushanfar:
AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge. 194:1-194:9
2024 CAD Contests at the ICCAD
- Shao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng:
Overview of 2024 CAD contest at ICCAD. 195:1-195:3 - Chung-Han Chou, Chih-Jen Hsu, Chi-An Wu, Kuan-Hua Tu, Kwangsoo Han, Zhou Li:
2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimization for a General Cost Function. 196:1-196:4 - Sheng-Wei Yang, Jhih-Wei Hsu, Ting-Wei Lee, Tzu-Hsuan Chen, Cindy Chin-Fang Shen:
2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop. 197:1-197:6 - Bing-Yue Wu, Rongjian Liang, Geraldo Pradipta, Anthony Agnesina, Haoxing Ren, Vidya A. Chhabria:
2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing Using ML Techniques and GPU Acceleration. 198:1-198:5 - Vidya A. Chhabria, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Bing-Yue Wu, Dooseok Yoon:
Strengthening the Foundations for IC Physical Design and ML EDA Research. 199:1-199:9
Swift LLMs: Easier Design: Faster Inference
- Lvcheng Chen, Ying Wu, Chenyi Wen, Shizhang Wang, Li Zhang, Bei Yu, Qi Sun, Cheng Zhuo:
An Agile Framework for Efficient LLM Accelerator Development and Model Inference. 200:1-200:9 - Youpeng Zhao, Jun Wang:
ALISE: Accelerating Large Language Model Serving with Speculative Scheduling. 201:1-201:9 - Shuzhang Zhong, Zebin Yang, Ruihao Gong, Runsheng Wang, Ru Huang, Meng Li:
ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding. 202:1-202:8 - Tiandong Zhao, Shaoqiang Lu, Chen Wu, Lei He:
ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity. 203:1-203:9
Time is Limited: Fast and Secure Neural Network Accelerators
- Kaisheng Ma, Zhanhong Tan, Zijian Zhu, Mengdi Wu:
LACO: A Latency-Constraint Offline Neural Network Scheduler towards Reliable Self-Driving Perception. 204:1-204:9 - Miao Wang, Shengbing Zhang, Sijia Wang, Zhao Yang, Meng Zhang:
OFT: An accelerator with eager gradient prediction for attention training. 205:1-205:9 - Jhon Ordoñez, Chengmo Yang:
Enhancing DNN Accelerator Integrity via Selective and Permuted Recomputation. 206:1-206:8
Private Machine Learning Inference
- Tianshi Xu, Shuzhang Zhong, Wenxuan Zeng, Runsheng Wang, Meng Li:
PrivQuant: Communication-Efficient Private Inference with Quantized Network/Protocol Co-Optimization. 207:1-207:9 - Jiangrui Yu, Wenxuan Zeng, Tianshi Xu, Renze Chen, Yun Liang, Runsheng Wang, Ru Huang, Meng Li:
FlexHE: A flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference. 208:1-208:9 - Hyunjun Cho, Jaeho Jeon, Jaehoon Heo, Joo-Young Kim:
APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits. 209:1-209:9 - Hyeri Roh, Woo-Seok Choi:
Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. 210:1-210:9
CIM is on the Run: Sparser and More Robust Designs
- Xuliang Yu, Tianwei Ni, Xinsong Sheng, Yun Pan, Lei He, Liang Zhao:
AESHA: Accelerating Eigen-decomposition-based Sparse Transformer with Hybrid RRAM-SRAM Architecture. 211:1-211:9 - Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka:
PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. 212:1-212:9 - Xiaomeng Wang, Jingyu He, Kunming Shao, Jiakun Zheng, Fengshi Tian, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui:
ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells. 213:1-213:9 - Xipeng Lin, Shanshi Huang, Hongwu Jiang:
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks. 214:1-214:9
Treasures in the Graphs: Efficient Designs for GNNs
- Enxin Yi, Jiarui Bai, Yijie Nie, Dan Niu, Zhou Jin, Weifeng Liu:
Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-Equipped FPGAs for GNNs. 215:1-215:9 - Yunki Han, Jaekang Shin, Gunhee Park, Lee-Sup Kim:
CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed Graph. 216:1-216:9 - Guoyu Li, Runzhou Zhang, Jun Yu, Kun Wang:
FLOP: A Flexible Memory-Optimized Processor for Parallel Graph Mining on FPGA. 217:1-217:9
More than Matrix Multiplication: Efficient Designs for Neural Networks
- Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin, Ulf Schlichtmann, Bing Li:
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. 218:1-218:8 - Junwoo Park, Kyeongho Lee, Jongsun Park:
TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration. 219:1-219:8 - Yuxuan Qiao, Fan Yang, Yecheng Zhang, Xiankui Xiong, Xiao Yao, Haidong Yao:
FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity. 220:1-220:9
Side Channels and Trojans
- Saleh Khalaj Monfared, Domenic Forte, Shahin Tajik:
RandOhm: Mitigating Impedance Side-channel Attacks using Randomized Circuit Configurations. 221:1-221:9 - Xingyu Tong, Guohao Chen, Min Wei, Zhijie Cai, Peng Zou, Zhifeng Lin, Jianli Chen:
Layout-level Hardware Trojan Prevention in the Context of Physical Design. 222:1-222:9 - Nezam Rohbani, Rouzbeh Pirayadi, Mohammad Arman Soleimani, Adrián Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad:
A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAM. 223:1-223:8 - Saleh Khalaj Monfared, Kyle Mitard, Andrew Cannon, Domenic Forte, Shahin Tajik:
LaserEscape: Detecting and Mitigating Optical Probing Attacks. 224:1-224:10
Advances in High-Level Synthesis and Optimized Components
- David Metz, Nico Reissmann, Magnus Själander:
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges. 225:1-225:9 - Chenwei Xiong, Cheng Liu, Huawei Li, Xiaowei Li:
HLSPilot: LLM-based High-Level Synthesis. 226:1-226:9 - Emmet Murphy, Lana Josipovic:
Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs. 227:1-227:9 - Dongsheng Zuo, Jiadong Zhu, Chenglin Li, Yuzhe Ma:
UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators. 228:1-228:9
Innovations in Neuromorphic Hardware and 3D Integration
- Boxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Sung Kyu Lim, Peng Li:
Spiking Transformer Hardware Accelerators in 3D Integration. 229:1-229:9 - Priyanjana Pal, Haibin Zhao, Tara Gheshlaghi, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic Circuits. 230:1-230:9 - Qinghang Zhao, Jiaqi Wang, Yixi Ji, Jinjian Wu, Guangming Shi:
An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors. 231:1-231:9 - Ning Lin, Songqi Wang, Xinyuan Zhang, Shaocong Wang, Yangu He, Woyu Zhang, Bo Wang, Jiankun Li, Mingzi Li, Binbin Cui, Yi Li, Jia Chen, Chunwei Xia, Wei Xuan, Xiaoming Chen, Dashan Shang, Zhongrui Wang:
LSMR: Synergy Randomness in Liquid State Machine and RRAM-based Analog-digital Accelerator. 232:1-232:9
Precision Matters: Improving the Robustness and Reconfigurability
- Minuk Hong, Hyeonuk Sim, Sugil Lee, Jongeun Lee:
FlexInt: A New Number Format for Robust Sub-8-Bit Neural Network Inference. 233:1-233:7 - Jinhao Li, Shan Huang, Jiaming Xu, Jun Liu, Li Ding, Ningyi Xu, Guohao Dai:
MARCA: Mamba Accelerator with Reconfigurable Architecture. 234:1-234:9 - Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris:
Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations. 235:1-235:9
Sparsity Matters: Sparse Computing Engines for Different Platforms
- Ziang Yin, Nicholas Gangi, Meng Zhang, Jeff Zhang, Z. Rena Huang, Jiaqi Gu:
SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution. 236:1-236:9 - Hongji Wang, Kun Wang, Yifan Zhang, Jun Yu:
FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGA. 237:1-237:9 - Shangran Lin, Xinrui Zhu, Baohui Xie, Tinghuan Chen, Cheng Zhuo, Qi Sun, Bei Yu:
RISCSparse: Point Cloud Inference Engine on RISC-V Processor. 238:1-238:8
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