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ORCIDIuliana P. Radu
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- affiliation: Inter-University Micro-Electronics Center (Imec), Leuven, Belgium
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Conference and Workshop Papers
- 2023
[c27]W.-C. Lin, H.-P. Huang, Kuo-Hsing Kao, Meng-Hsueh Chiang, Darsen D. Lu, Wei-Chou Hsu, Yeong-Her Wang, William Cheng-Yu Ma, Hann-Huei Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang, Iuliana P. Radu:
MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. ESSDERC 2023: 9-12- [c26]H.-L. Chiang, Richard A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu:
How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. VLSI Technology and Circuits 2023: 1-2 - [c25]A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo
, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, R. Li, Iuliana P. Radu, P. Van Dorpe, Kristiaan De Greve:
Comprehensive 300 mm process for Silicon spin qubits with modular integration. VLSI Technology and Circuits 2023: 1-2 - [c24]Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu:
Building high performance transistors on carbon nanotube channel. VLSI Technology and Circuits 2023: 1-2 - [c23]Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu:
Scaled contact length with low contact resistance in monolayer 2D channel transistors. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c22]Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu:
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits 2022: 230-231 - [c21]Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana P. Radu, H.-S. Philip Wong, Han Wang:
Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. VLSI Technology and Circuits 2022: 290-291 - [c20]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi:
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331 - [c19]Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu:
Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. VLSI Technology and Circuits 2022: 403-404 - 2021
- [c18]Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor:
Circuit models for the co-simulation of superconducting quantum computing systems. DATE 2021: 968-973 - [c17]Dennis Lin, Xiangyu Wu, Vivek Mootheri, Daire Cott, Benjamin Groven, Pierre Morin, Inge Asselberghs, Iuliana P. Radu:
On MX2-based metal-oxide-semiconductor device capacitance-voltage characteristics and dual-gate operation. DRC 2021: 1-2 - [c16]Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor:
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSCIRC 2021: 63-66 - [c15]Benjamin Gys, Fahd A. Mohiyaddin, Rohith Acharya, Roy Li, Kristiaan De Greve, Georges G. E. Gielen, Bogdan Govoreanu, Iuliana P. Radu, Francky Catthoor:
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. ESSDERC 2021: 63-66 - [c14]Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu:
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. VLSI Circuits 2021: 1-2 - [c13]Nard I. Dumoulin Stuyck, Roy Li, Clement Godfrin, Asser Elsayed, Stefan Kubicek, Julien Jussot, B. T. Chan, Fahd A. Mohiyaddin, Mohamed Shehata, George Simion, Yann Canvel, Ludovic Goux, Heyns Heyns, Bogdan Govoreanu, Iuliana P. Radu:
Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process. VLSI Circuits 2021: 1-2 - 2020
- [c12]Alexander Grill, Erik Bury, Jakob Michl, Stanislav Tyaginov, Dimitri Linten, Tibor Grasser, Bertrand Parvais, Ben Kaczer, Michael Waltl, Iuliana P. Radu:
Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures. IRPS 2020: 1-6 - [c11]Jakob Michl, Alexander Grill, Dieter Claes, Gerhard Rzepa, Ben Kaczer, Dimitri Linten, Iuliana P. Radu, Tibor Grasser, Michael Waltl:
Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures. IRPS 2020: 1-6 - 2019
- [c10]Yashwanth Balaji, Quentin Smets, Dennis Lin, I. Asselberghs, Iuliana P. Radu, Guido Groeseneken:
Tunnel FETs using Phosphorene/ReS2 heterostructures. DRC 2019: 113-114 - 2018
- [c9]Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Towards high-performance polarity-controllable FETs with 2D materials. DATE 2018: 637-641 - [c8]Iuliana P. Radu:
Spin-based majority gates for logic applications. DRC 2018: 1-2 - [c7]Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. DRC 2018: 1-2 - 2017
- [c6]Tarun Agarwal, Bart Soree, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Marc M. Heyns, Wim Dehaene:
Material selection and device design guidelines for two-dimensional materials based TFETs. ESSDERC 2017: 54-57 - [c5]Yashwanth Balaji, Quentin Smets, Cesar J. Lockhart de la Rosa, Anh Khoa Augustin Lu, Daniele Chiappe, Tarun Agarwal, Dennis Lin, Cedric Huyghebaert, Iuliana P. Radu, Dan Mocuta, Guido Groeseneken:
Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures. ESSDERC 2017: 106-109 - [c4]Tom Schram, Quentin Smets, Benjamin Groven, M. H. Heyne, E. Kunnen, A. Thiam, Katia Devriendt, Annelies Delabie, Dennis Lin, M. Lux, Daniele Chiappe, I. Asselberghs, S. Brus, Cedric Huyghebaert, S. Sayan, A. Juncker, Matty Caymax, Iuliana P. Radu:
WS2 transistors on 300 mm wafers with BEOL compatibility. ESSDERC 2017: 212-215 - 2016
- [c3]Tarun Agarwal, Iuliana P. Radu, Praveen Raghavan, Gianluca Fiori, Aaron Thean, Marc M. Heyns, Wim Dehaene:
Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. ESSCIRC 2016: 55-58 - 2015
- [c2]Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean:
Area and routing efficiency of SWD circuits compared to advanced CMOS. ICICDT 2015: 1-4 - 2014
- [c1]Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean:
System-level assessment and area evaluation of Spin Wave logic circuits. NANOARCH 2014: 25-30
Informal and Other Publications
- 2019
- [i2]Giacomo Talmelli, Thibaut Devolder, Nick Träger, Johannes Förster, Sebastian Wintz, Markus Weigand, Hermann Stoll, Marc M. Heyns, Gisela Schütz, Iuliana P. Radu, Joachim Gräfe, Florin Ciubotaru, Christoph Adelmann:
Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing. CoRR abs/1908.02546 (2019) - 2016
- [i1]Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu:
Non-volatile spin wave majority gate at the nanoscale. CoRR abs/1612.02170 (2016)
Coauthor Index
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