27. VLSI Design 2014: Munbai, India


Session A1: 3D Test

Session A2: SAT Application

Session A3: Design Verification

Session A4: Test Generation

Session A5: Reliable Circuits

Session A6: Memory

Session B1: Real-Time Systems

Session B2: Embedded Platform

Session B3: Architectures

Session B4: Network-on-Chip

Session B5: MPSoCs

Session B6: Embedded Systems

Session C1: FPGA

Session C2: Low-Power Design

Session C3: Digital Design

Session C4: Physical Design

Session C5: Modeling and Simulation

Session C6: Modeling and Analysis

Session D1: RF Circuits

Session D2: LP Circuits

Session D3: MEMS/Biochips

Session D4: Analog Circuits I

Session D5: Emerging Technologies

Session D6: Analog Circuits II

maintained by Schloss Dagstuhl LZI at University of Trier