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CICC 2007: San Jose, California, USA
- Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. IEEE 2007, ISBN 978-1-4244-1623-3
- Roberto Canegallo, Alberto Fazzi, Luca Ciccarelli, Luca Magagni, Federico Natali, Pier Luigi Rolandi, Erik Jung
, Léa Di Cioccio, Roberto Guerrieri:
3D Capacitive Interconnections for High Speed Interchip Communication. 1-8 - Zheng Xu, Kenneth L. Shepard:
Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking. 9-12 - Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda:
Wideband Inductive-coupling Interface for High-performance Portable System. 13-20 - Larry Wissel, Harold Pilo, Chris LeBlanc, Xiaopeng Wang, Steve Lamphier, Michael Fragano:
A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology. 21-24 - Vinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj:
A Disturb Decoupled Column Select 8T SRAM Cell. 25-28 - Jiajing Wang, Benton H. Calhoun:
Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM. 29-32 - Shin-ichi O'Uchi
, Meishoku Masahara
, Kunihiro Sakamoto
, Kazuhiko Endo
, Yongxun Liu
, Takashi Matsukawa
, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. 33-36 - Robert M. Houle:
Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times. 37-40 - Weimin Wu, Xin Li, Gennady Gildenblat, Glen O. Workman, Surya Veeraraghavan, Colin C. McAndrew, Ronald van Langevelde
, Geert D. J. Smit
, Andries J. Scholten
, Dirk B. M. Klaassen, Josef Watts:
PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs. 41-48 - Benjamín Iñíguez, Antonio Lázaro
, Hamdy Abd Elhamid
, Oana Moldovan
, Bogdan Nae
, Jaume Roig, David Jiménez
:
Charge-Based Compact Modeling of Multiple-Gate MOSFET. 49-56 - Ning Lu, Matthew Angyal, Gerald Matusiewicz, Vincent J. McGahay, Theodorus E. Standaert:
Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology. 57-60 - Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura:
A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling. 61-64 - Kentaro Yamamoto, Anthony Chan Carusone
, Francis P. Dawson:
A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR. 65-68 - Alex Jianzhong Chen, Yong Ping Xu:
A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC. 69-72 - Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes:
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. 73-76 - Jian-Yi Wu, Raj Subramoniam, Zhenyong Zhang, Ali Djabbari, Peter Holloway, Franco Maloberti, Masood Yousefi, Mehmat Aslan, Hua Hong, Ahmad Bahai:
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections. 77-80 - Jason C. Chen, Chun-Fu Shen, Shao-Yi Chien
:
Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders. 81-84 - Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang:
CAD Techniques for Power Optimization in Virtex-5 FPGAs. 85-88 - Kyung Joon Han, Nigel Chan, Sungrae Kim, Ben Leung, Volker Hecht, Brian Cronquist, Danny Shum, Armin Tilke, Laura Pescini, Martin Stiftinger, Ronald Kakoschke:
Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation. 89-91 - Tim Tuan, Tom Strader, Steve Trimberger:
Analysis of Data Remanence in a 90nm FPGA. 93-96 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO. 97-100
- Matthias Locher, Mark Tomesen, Jeroen Kuenen, Anton Daanen, Henk Visser, Bert Essink, Peter Paul Vervoort, Manjo Nijrolder, Rob Kopmeiners, William Redman-White, Richard A. H. Balmford, Rachid El Waffaoui:
A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e). 101-105 - Yang Xu, Kevin Wang, Tim Pals, Aristotele Hadjichristos, Kamal Sahota, Charles J. Persico:
A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver. 107-110 - Wenting Wang, Shuzuo Lou, Kay W. C. Chui, Sujiang Rong, Chi Fung Lok, Hui Zheng, Hin-Tat Chan, Adam S. W. Man, Howard C. Luong
, Vincent Kin Nang Lau
, Chi-Ying Tsui
:
Single-Chip UHF RFID reader in 0.18- μm CMOS. 111-114 - Reid R. Harrison:
A Versatile Integrated Circuit for the Acquisition of Biopotentials. 115-122 - Arjang Hassibi, Aydin Babakhani, Ali Hajimiri
:
A Spectral-Scanning Magnetic Resonance Imaging (MRI) Integrated System. 123-126 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model. 127-130 - Hidekuni Takao, Masaki Yawata, Ryo Kodama, Kazuaki Sawada, Makoto Ishida:
Multi-functional Monolithic-MEMS Tactile Imager Using Flexible Deformation of Silicon IC. 131-134 - Stephen K. Sunter, Aubin Roy:
Testing SerDes beyond 4 Gbps - changing priorities. 135-138 - Adam Healey:
Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane Ethernet. 139-144 - Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu:
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device. 145-148 - Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev:
Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. 149-152 - Jeff Rearick:
Embedded Test Features for High-Speed Serial I/O. 153-156 - Keith A. Jenkins, Kenneth L. Shepard, Zheng Xu:
On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks. 157-160 - Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter. 161-164 - Ebrahim Ghafar-Zadeh, Mohamad Sawan:
A 0.18 μm CMOS Capacitive Detection Lab-on-Chip. 165-172 - Edward K. Lee, Phil Hess, John Gord, Howard Stover, Patrick Nercessian:
A 400MHz RF Transceiver for Implantable Biomedical Micro-Stimulators. 173-176 - Paras Samsukha, Steven L. Garverick:
A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff. 177-180 - Taeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan:
A Low Power Carbon Nanotube Chemical Sensor System. 181-184 - Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jin Park, Jae-Whui Kim:
A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC. 185-188 - Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. 189-192 - Yangjin Oh, Boris Murmann
:
A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration. 193-196 - Behzad Saeidi:
A Fourth Order Elliptic Low-Pass Filter with Wide Range of Programmable Bandwidth, Using Four Identical Integrators. 197-200 - Marc Keppler, Donald Thelen:
An Idle-Tone Free Dynamic Element Matching Algorithm. 201-204 - Rui Yu, Yong Ping Xu:
A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter. 205-208 - N. Yoshii, K. Mizutani, Yasuhiro Sugimoto:
A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain. 209-212 - Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang:
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. 213-216 - Yi-Chung Chen, Yi-Chang Wu, Po-Chiun Huang:
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver. 217-220 - David E. Duarte, George L. Geannopoulos, Usman Mughal, Keng L. Wong, Greg Taylor:
Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process. 221-224 - Sayeed A. Badrudduza, Lawrence T. Clark:
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. 225-228 - Shweta Srivastava, Jaijeet S. Roychowdhury:
Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations. 229-232 - Toshikazu Suzuki, Hiroyuki Yamauchi
, Katsuji Satomi, Hironori Akamatsu:
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. 233-236 - Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev:
Dynamic Data Stability in Low-power SRAM Design. 237-240 - Tony Tae-Hyoung Kim, Jason Liu, Chris H. Kim:
An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement. 241-244 - Troy Ruud, Bryce Rasmussen, Bruce Greenwood, Matthew Tyler:
Solution to ESD Induced Pocket Isolation Failure in Multi Well CMOS. 245-248 - Hongmei Liao, Li Song, Nickhil Jakatdar, Riko Radojcic:
Integration of CMP Modeling in RC Extraction and Timing Flow. 249-252 - Jeong-Il Kim, Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Byunghoo Jung, Dimitrios Peroulis
:
Integrated Inductor Actively Engaging Metal Filling Rules. 253-256 - David Levacq, Takuya Minakawa, Makoto Takamiya, Takayasu Sakurai:
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. 257-260 - Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino:
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. 261-264 - Simar Maangat, Toan Nguyen, Wilson Wong, Sergey Y. Shumarayev, Tina Tran, Tim Hoang, Richard Cliff:
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. 265-267 - Vincent von Kaenel, Toshinari Takayanagi:
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. 269-272 - Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. 273-276 - Thomas Suttorp, Ulrich Langmann:
A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery. 277-280 - Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue
:
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. 281-284 - Ali Kiaei, Babak Matinpour, Ahmad Bahai, Thomas H. Lee:
A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links. 285-288 - Chi-Shiung Lin, Yu-Chun Lin, Shyh-Jye Jou, Mun-Tian Shiou:
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System. 289-292 - Wei-Zen Chen, Shih-Hao Huang:
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector. 293-296 - Yi-Bin Hsieh, Yao-Huang Kao:
A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes. 297-300 - Vishak Venkatraman, Wayne P. Burleson:
An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects. 301-304 - Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. 305-308 - Lin Zhang, Berkehan Ciftcioglu, Hui Wu:
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking. 309-312 - Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim:
A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. 313-316 - J. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro
:
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration. 317-320 - Youn-Jae Kook, Jipeng Li, Bumha Lee, Un-Ku Moon:
Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique. 321-324 - Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V 10b 30MSPS Switched-RC Pipelined ADC. 325-328 - Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta
:
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. 329-332 - Samad Sheikhaei, Shahriar Mirabbasi, André Ivanov:
A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS. 333-336 - Ivan Bogue, Michael P. Flynn:
A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. 337-340 - Afshin Haftbaradaran, Kenneth W. Martin:
A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems. 341-344 - Takashi Kawamoto, Tomoaki Takahashi, Hiromitsu Inada, Takayuki Noto:
Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Applications. 345-348 - Hiroshi Kodama, Hiroyuki Okada, Hiromu Ishikawa, Akio Tanaka
:
Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization. 349-352 - Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon:
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. 353-356 - Sander L. J. Gierkink:
A 2.5Gb/s Burst-Mode CDR based on a 1/8th rate Dual Pulse Ring Oscillator. 357-360 - Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram:
Digitally-Enhanced Phase-Locking Circuits. 361-368 - Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim:
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. 369-372 - Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park:
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. 373-376 - Marnie Wong, Bertan Bakkaloglu
, Sayfe Kiaei:
A low noise buck converter with a fully integrated continuous time ΣΔ modulated feedback controller. 377-380 - Jeremy Holleman, Brian P. Otis, Chris Diorio:
A compact pulse-based charge pump in 0.13 μm CMOS. 381-384 - Song Guo, Hoi Lee:
An Efficiency-Enhanced Integrated CMOS Rectifier with Comparator-Controlled Switches for Transcutaneous Powered Implants. 385-388 - Elad Alon, Mark Horowitz:
Integrated Regulation for Energy-Efficient Digital Circuits. 389-392 - Raymond E. Barnett, Jin Liu:
An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control. 393-396 - Yu-Shiang Lin, Dennis Sylvester, David T. Blaauw:
A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems. 397-400 - Jaesik Lee, Joseph Weiner, Hsin-Hung Chen, Yves Baeyens, Vladimir Aksyuk
, Young-Kai Chen:
CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems. 401-404 - J. W. McPherson:
Reliability Trends with Advanced CMOS Scaling and The Implications for Design. 405-412 - Ghavam G. Shahidi:
Evolution of CMOS Technology at 32 nm and Beyond. 413-416 - Mukesh Khare:
High-K/Metal Gate Technology: A New Horizon. 417-420 - Muhannad S. Bakir, Bing Dang, James D. Meindl:
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. 421-428 - Randy Torrance, Dick James:
Reverse Engineering in the Semiconductor Industry. 429-436 - Brett A. Swanson
, Erika Van Baelen, Mark Janssens, Michael Goorevich, Tony Nygard, Koen Van Herck:
Cochlear Implant Signal Processing ICs. 437-442 - Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo:
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory. 443-446 - Run Chen, Liyuan Liu, Dongmei Li:
A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS. 447-450 - Flavio Carbognani, Simon Haene, Manuel Arrigo, Claudio Pagnamenta, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication. 451-454 - Ruwan N. S. Ratnayake, Aleksandar Kavcic, Gu-Yeon Wei:
A High-Throughput Maximum a posteriori Probability Detector. 455-458 - Ahmad Darabiha, Anthony Chan Carusone
, Frank R. Kschischang
:
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS. 459-462 - Firooz Aflatouni, Omeed Momeni, Hossein Hashemi:
A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS. 463-466 - Deyi Pi, Byung-Kwan Chun, Payam Heydari:
A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers. 467-470 - Sorin P. Voinigescu, Ricardo Andres Aroca, Timothy O. Dickson, Sean T. Nicolson, Theodoros Chalvatzis, Pascal Chevalier
, Patrice Garcia, Christophe Gamier, Bernard Sautreuil:
Towards a sub-2.5V, 100-Gb/s Serial Transceiver. 471-478 - Bryan Casper, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Mozhgan Mansuri:
Future Microprocessor Interfaces: Analysis, Design and Optimization. 479-486 - Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz:
Time-Variant Characterization and Compensation of Wideband Circuits. 487-490 - Moon-Jung Kim, Henrik Icking, Harald Gossner
, Thomas H. Lee:
High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications. 491-494 - James Victory, Zeqin Zhu, Q. Zhou, Weimin Wu, Gennady Gildenblat, Zhixin Yan, Juan Cordovez, Colin C. McAndrew, F. Anderson, Jeroen C. J. Paasschens, Ronald van Langevelde
, P. Kolev, R. Cherne, C. Yao:
PSP-Based Scalable MOS Varactor Model. 495-502 - Bertrand Parvais
, S. Hu, Morin Dehan, Abdelkarim Mercha, Stefaan Decoutere:
An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs. 503-506 - Sharad Kapur, David E. Long, Robert C. Frye, Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou, Bigchoug Hung:
Synthesis of Optimal On-Chip Baluns. 507-510 - Wenping Wang, Vijay Reddy, Anand T. Krishnan, Rakesh Vattikonda, Srikanth Krishnan, Yu Cao:
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology. 511-514 - Ajay Balankutty, T. C. Chih, C. Y. Chen, Peter R. Kinget
:
Mismatch Characterization of Ring Oscillators. 515-518 - Carlos Galup-Montoro
, Márcio Cherem Schneider, Ana Isabela Araújo Cunha, Fernando Rangel de Sousa
, Hamilton Klimach, Osmar Franca Siebel:
The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design. 519-526 - Junghwan Han
, Ranjit Gharpurey:
A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance Reuse. 527-530