default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCICC 2025: Boston, MA, USA
- IEEE Custom Integrated Circuits Conference, CICC 2025, Boston, MA, USA, April 13-17, 2025. IEEE 2025, ISBN 979-8-3315-1745-8
- Yifei Xia
, Zhixing Zhang, Shuaizhe Ma, Yuanhao Yao, Ruixuan Yang, Yuye Yang, Jianyu Yang, Li Geng, Dan Li:
A CMOS Low-Noise Fast-Settling BM-TIA with CM-Post-Amplifier Chip Connectivity for 50G-PON. 1-3 - Gyeong-Gu Kang, Minjie Chen, Hyun-Sik Kim:
A 5V-Input, 12.5-to-45V-Output Reconfigurable Hybrid Boost Converter with an SC-Based Parallel Auxiliary Cell Achieving 96.8% Peak Efficiency. 1-3 - Zexin Wang, Lingxin Meng, Menglian Zhao, Mengyu Li, Shuang Song, Zhichao Tan:
A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback. 1-3 - Armin Tajalli, Cosimo Aprile, Milad Ataei, Rolf Beerwerth, Dario Carneli, Maik Fuhs, Kiarash Gharibdoust, Ali Hormati, James Hudner, Victor Perrin, Amin Shokrollahi, Richard Simpson, Andrew Stewart, David Stauffer, Giuseppe Surace, Roger Ulrich, Patrick Urban, Mark Venneborger, Anant Singh:
A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling. 1-3 - Han-Mo Ou, Gene Lee, Naresh Shanbhag:
Forward Error Correction Requirements for Data Center Connectivity. 1-3 - Gourab Barik, Harshit Naman, Yudhajit Ray, Shreyas Sen:
TD-dAJC: A 2pJ/Pixel Time-Domain Weight and Integrating-MAC Based Direct-Analog-to-MJPEG Compression for Video Sensor Nodes. 1-3 - Yajie Zhao, Yongjie Ye, Shaokai Yuan, Yajie Qin:
A 133.6-µW 1kHz-BW Multi-Bit 2nd-Order Incremental ADC Achieving 115.4-dB SNDR with Low-Cost Coarse-Sorting DEM and Zip-Extended-Counting. 1-3 - Ramin Javadi, Tejasvi Anand:
A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET. 1-3 - Xining Zhang, Yuxiang Tang, Yaohua Pan, Wenhui Qin, Jian Ye, Shaoyu Ma, Yun Sheng, Zhiliang Hong, Jiawei Xu:
A 14-Cell Battery Monitoring AFE with 1mV Total Measurement Error and Integrated Electrochemical Impedance Spectroscopy. 1-3 - Hongkun Li, Yiyang Shu, Xun Luo:
A 28-GHz 189.2-dBc/Hz FoM 360° Phase-Shifting Quadrature Oscillator Without Phase Ambiguity Achieving 0.13° RMS Phase Error Under 2° Phase Resolution. 1-3 - Niccolò Villaggi, Yuqi Liu, Tzu-Yuan Huang, Sensen Li, Taiyun Chi, Hua Wang:
A 27-39GHz 48Gbit/s 8-Channel Phased Array Transceiver Frontend with Broadband TX/RX Co-Design Optimization. 1-3 - Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone:
High-Entropy Analog-Based Strong PUF Reaching 166 F2/Bit Area-to-Entropy-Ratio. 1-3 - Fengshi Tian, Jinbo Chen, Kunming Shao, Zilu Liu, Jiakun Zheng, Hui Wu, Chaoming Fang, Xiaomeng Wang, Ziyang Shen, Pingcheng Dong, Yuan Yao, Xuliang Wang, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting Cheng:
E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables. 1-3 - Baochuang Wang, Lin Cheng:
A 94.5%-Peak-Efficiency Dual-Path Single-Inductor Dual-Output Converter with Reduced Inductor Current and Output Voltage Ripple. 1-3 - Junlong Gong, Wei Deng, Shulin Yao, Haikun Jia, Xinyu Jiang, Xiangyu Nie, Dongfang Li, Hongliang Wu, Chuanming Zhu, Xiangrong Huang, Baoyong Chi:
A 22-to-32 GHz 4-Beam 32-Element Polarization Reconfigurable Fully-Connected Fully-Bidirectional MIMO Transceiver for Emerging Space-Air-Ground-Sea Integrated Network. 1-3 - Haoyu Li, Boyang Wang, Hongjiang Chen, Sai-Weng Sin, Yutao Peng, Xizhu Peng, He Tang, Chao Fan, Liang Qi, Rui Paulo Martins, Mingqiang Guo:
A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. 1-3 - Xiongjie Zhang, Xinman Li, Yang Jiang, Zhangming Zhu, Rui Paulo Martins, Pui-In Mak:
A 98.5% Peak Efficiency 2/3-Phase Buck-or-Boost Converter With VCR-Independent Loss Optimization and Unconditional RHP Zero Elimination Achieving 2.76A/mm2-Current-Density and 6.5µs Recovery. 1-3 - Jialei Wu, Simeng Yin, Yixin Zhou, Jianye Li, Kai Li, Xiaoyan Shen, Tinghui Sun, Xinlong Zhang, Keping Wang:
A Tripolar Stimulator with Return-Electrode-Based Charge-Pack Injection Technique for Charge Imbalance Correction in Spatiotemporal Stimulation. 1-3 - Yuanzhe Zhao, Heng Xie, Zijian Wang, Chunlin Tian, Li Li, Yan Zhu, R. P. Martins, Chi-Hang Chan, Minglei Zhang:
A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs. 1-3 - Qingqing Min, Jingyi Yuan, Lin Cheng:
A Zero-Voltage-Switching Buck Converter with Conduction-Loss-Minimized ZVS Operation and Auxiliary Inductor Transient Reuse Technique Achieving up to 8.3% Efficiency Improvement and 42% Voltage Droop Reduction. 1-3 - Min Suk Lee, Zhaoyi Liu, Abhinav Uppal, Jiahao Song, Akshay Paul, Florian Chapotot, Esra Tasali, Yuchen Xu, Gert Cauwenberghs:
In-Ear EEG Auditory Neurofeedback Towards Unobtrusive Sleep Enhancement. 1-7 - Jyotindra R. Shakya, Gabor C. Temes, Faraz Adin:
A 16 GΩ Input Impedance Amplifier with Flicker Noise Reduction for Neural Recording Applications. 1-3 - Jieyu Li, Weifeng He, Boran Jiang, Xinyu Wang, Guanghui He, Dingxuan Liu, Mingoo Seok:
SparseTrim: A Neural Network Accelerator Featuring On-Chip Decompression of Fine-Grained Sparse Model with 10.1TOPS/W System Energy Efficiency. 1-3 - Zeguo Liu, Zhiren Luo, Xiangan You, Dongjie Ye, Weiyi Tang, Qinyang Wang, Qidong Wang, Jianliang Shen, Lin Cheng:
A 100A 48-60V to 1V Hybrid LLC Resonant Converter with 51mV Droop for a 70A/20ns Load Transient. 1-3 - Urs Hecht, Philipp Scholz, Patrick Kurth, Frowin Buballa, Helia Ordouei, Friedel Gerfers:
A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI. 1-3 - Bo Liu, Xingyu Xu, Yang Zhang, Xilong Kang, Qingwen Wei, Zihan Zou, Jun Yang, Hao Cai, Xin Si:
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. 1-3 - Jimin Koo, Sein Oh, Yoontae Jung, Vincent Lukito, Sohmyung Ha, Minkyu Je:
A 6µW ECG-Recording ΔΣ Modulator with Internal-Capacitor-Flipping Technique for 34Vpp Common-Mode-Interference (CMI) Tolerance and 1Vpp Input Range. 1-3 - Hong Liao, Wentao Ma, Xiaoxu Yang, Jianfang Nie, Bingfang Wang, Zhiqiang Chang, Yin Fang, Miao Meng:
An Implantable Fully-Packaged Current-Controlled Wireless Near-Adiabatic Neural Stimulator Achieving 71.7% Peak Efficiency and 13.5% Efficiency Variation Across Supported Stimulation Current Range. 1-3 - Yuanzhe Zhao, Yang Wang, Yuheng Wang, Heng Xie, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Shouyi Yin, Minglei Zhang:
A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. 1-3 - Sangsu Jeong, Huiwon Yun, Dongkwon Lee, Sunwoo Lee, Minyoung Kang, Dongsuk Jeon:
An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS. 1-3 - Xiaofeng Hu, HanGyeol Mun, Jian Meng, Yuan Liao, Amitesh Sridharan, Jae-sun Seo:
A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization. 1-3 - Yonghee Chang, Wei Wang, Yiwei Zou, Kaiyuan Yang:
RPG-HBC: Reconfigurable Passive Galvanic Human Body Communication for Bioelectronic Implants Under Varying Channel Conditions. 1-3 - Srivatsa Rangachar Srinivasa, Prerna Budhkar, Gauthaman Murali, Vui Seng Chua, Paolo A. Aseron, Vinayak Honkote, Ravi R. Iyer, Nilesh Jain, Dileep John Kurian, Anuradha Srinivasan, Tanay Karnik:
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. 1-3 - Ahmed Abdelaal, John G. Kauffman, Joachim Becker, Matteo Dalla Longa, Francesco Conzatti, Maurits Ortmanns:
A Calibration-free 80MHz CT DSM Using Dual Quantization and ISI Shuffler Achieving 106.2dB SFDR. 1-3 - Yifeng Zhou, Xin Hao, Qinchao Cai, Lei Liao, Zhuojun Chen:
A Reconfigurable Potts Machine with Successive Boundary Approximation Annealing for Solving Combinatorial Optimization Problems. 1-3 - Sanghyeon Cho, Jeonghoon Cho, Hyunjoong Kim, You Jang Pyeon, Dong Kwan Kang, Yonggi Kim, Eui-Sung Jung, Hoon Eui Jeong, Jae Joon Kim:
An Energy-Efficient Healthcare Chest Patch Interface with Multi-Domain On-Sensor Computing and Inter-Sensor Windowing. 1-3 - Yanquan Luo, Lu Jie, Nan Sun:
A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback. 1-3 - Tahmida Islam, Junkyu Kim, Hanzhao Yu, Chris H. Kim:
Tracking Fmax Degradation of a RISC-V CPU with Synthesizable Odometer Aging Sensors. 1-6 - Huanyu Ge, Haikun Jia, Wei Deng, Baoyong Chi:
A 22.0-to-28.4GHz 192.2dBc/Hz FoM and 206.2dBc/Hz FoMA Dual-Core VCO Using Circular-Inverse-Class-F Topology Under Standard Supply Voltage in 65nm CMOS Process. 1-3 - Rentao Wan, Yichen Xu, Dong-Woo Jee, Mingoo Seok:
AJPEG: A 26.4-pJ/pixel, 252-fps, 128×128 Image Sensor with an In-Sensor Analog DCT Processor for Data Compression. 1-3 - Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi:
A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel. 1-3 - Xingchen Chao, Yunqiang Xu, Qiang Yu, Zheng Zhu, Sanfeng Zhang, Qiang Li:
A Timing-Robust 10b 13GS/s ADC with Analog Fourier Transform Based Frequency Interleaving. 1-3 - Yu-Chen Kuo, Yu-Ting Huang, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Xi Zhu:
A Pseudo-4-Phase Buck Converter with 94.1 % Efficiency, 1mV Output Ripple and Fast Transient Response. 1-3 - Bodhisatwa Sadhu, Kevin Tien, Sudipto Chakraborty, David J. Frank, Pat Rosno, Daniel Moertl, Mark Yeck, John F. Bulzacchelli, Daniil Frolov, Devin Underwood, Ken Inoue, Christian W. Baks, Daniel Ramirez, Jeremy Ekman, Ryan Black, Timothy J. Schmerbeck, Ray Richetta, Dereje Yilma, Andrew Davies, Joseph A. Glick, Dorothy Wisnieff, Bryce Snell, John Timmerwilke, Raphael Robertazzi, George Zettles, Scott Lekuch, Scott Willenborg, Brian P. Gaucher, Daniel J. Friedman:
Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. 1-3 - Kai Li, Jialei Wu, Keping Wang:
A 6-18-GHz Reflectionless Blocker-Canceling Mixer-First Receiver with Maximum 55.6-dB Out-of-Band Rejection for Satellite Communication Systems. 1-3 - Weiping Wu, Xun Bao, Shi Chen, Jingze Wang, Shulan Chen, Yan Wang, Lei Zhang:
A CMOS 228-324GHz RF Domain Quadrature Receiver with a Broadband Harmonic-Enhanced LO Generator. 1-3 - Zhenghong Chen, Braden E. Desman, Anjali Agrawal, Will Farrell, Jim Owens, Daniel S. Truesdell, Benton H. Calhoun:
ISPI: A 2-Wire Improved Serial Peripheral Interface with Automatic Routing Algorithm for 2-D In-Textile Distributed Computing and Storage Systems. 1-3 - Xiaosen Liu, Xichen Sun, Haozhe Zhang, Yan Wang:
3D-IC Chiplet Integrated Power Supply with LDO, SCVR, and Buck DC-DC Converter. 1-8 - Byeongjin Son, Heungsik Eum, Hyeonjun Pi, Youngcheol Chae:
A Resistive Dynamic Bias Comparator with Flying Capacitors Achieving 129µVrms Input-Referred Noise at 1GS/s in 28nm FD-SOI. 1-3 - Jung-Jin Park, Julian Arenas, Kevin Patino-Sosa, Visvesh S. Sathe:
A 0.14µJ Per-Acquisition Frequency Domain GPS Correlator Using Adaptive Compressive Sampling. 1-3 - Yuanfei Wang, Zhiyuan Zhang, Ziyang Zhong, Yihan Zhang, Rui Paulo Martins, Mo Huang:
An SC-first Hybrid SCVR with 4xCF Continuously Scalable-Conversion Ratio SC Achieving 92.5% Peak Efficiency. 1-3 - Zahra Mohseni, Sajjad Sabbaghi, Hai Yu, Peixin Han, Qun Jane Gu:
D-Band Dicke Switch Based Passive Imager with 0.13K NETD in 28nm CMOS Technology. 1-3 - Tzu-Han Wang, Chenyang Li, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh Sathe, Shaolan Li:
A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression. 1-3 - Yuxiang Tang, Yijie Li, Kaiwen Zhou, Qi Luo, Xining Zhang, Yongda Ma, Zhiliang Hong, Jiawei Xu:
A-117.1dB THD Audio Decoder Utilizing Single Vector Quantizer for Simultaneous Mismatch and ISI Shaping. 1-3 - Giyeong Heo, Younghwan Chang, Yong-Un Jeong, Jaekwang Yun, Jusung Lee, Shin-Hyun Jeong, Sanghyuk Seo, Suhwan Kim:
An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface. 1-3 - Liqun Feng, Xuansheng Ji, Qianxian Liao, Longhao Kuang, Yunzhao Nie, Jiahao Zhao, Woogeun Rhee, Zhihua Wang:
A 0.5V 0.55mm2 Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT applications. 1-3 - Chaeeun Lee, Jongho Kim, Jintae Kim:
A 17.4fJ/conv.-step, 202µm2, 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator. 1-3 - H. Fukutome, J. Kim, Joonghan Shin, J. Kim, Youngsoo Lee, S. Chae, B. Eom, Y. S. Nam, Minseong Lee, Sanghyun Ha, E. G. Chung, Sung-Hoon Lee, Sang Kim, K. H. Cho, K. W. Lee, D. W. Kim, H.-J. Cho, K. Rim, J. Song:
Demonstration of Logic-Block Performance-Power-Area Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node. 1-6 - Zhaoqing Wang, Yichen Xu, Suhwan Kim, Nachiket V. Desai, Minxiang Gong, Ram Krishnamuthy, Xin Zhang, Mingoo Seok:
A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control. 1-3 - Xinling Yue, Wenyu Peng, Sijun Du:
A Fully Integrated Adaptive-MPP-Shifting Rectifier for Piezoelectric Energy Harvesting Outputting 580µW at 10V-VOC. 1-3 - Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Robert Bogdan Staszewski, Fujiang Lin, Liheng Lou, Yizhe Hu:
A 0.0022 mm2, 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping. 1-4 - Yuyu Lin, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan:
A 48x OSR 105.4-dB SNDR 24-kHz BW CT Zoom ADC with Reset Tri-level DWA and On-chip Negative-R Calibration. 1-3 - Jianxin Yang, Rui Paulo Martins, Mo Huang:
25-nA Modified Hybrid Ladder Converter with Efficient Output-Capacitor Charge Recycling and 90% Battery Lifetime Extension. 1-3 - Xueke Cai, Tong Zhang, Weihao Jie, Yanling Zheng, Deyong Li, Yiwen Zhang, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang:
BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9dB at 3GHz with a Ring Oscillator. 1-3 - Zhiguo Tong, Wenjie Yang, Shousheng Han, Junwei Huang, Xiangyu Mao, Yan Lu:
Where is the Inductor: A Review and Comparison of the Hybrid DC-DC Buck Topologies. 1-8 - Ziyuan Guo, Wei Deng, Weiqi Zheng, Haikun Jia, Hongliang Wu, Qiuyu Peng, Fuyuan Zhao, Junyang Yin, Dongze Li, Baoyong Chi:
A 104-to-132 GHz 16-way Power Amplifier Using Enhanced Magnetic Coupling Cavity Achieving 21.2 dBm Output Power in 28nm Bulk CMOS. 1-3 - Yaoru Hou, Haoran Du, Jiongzhe Su, Yibo Liu, Zhenghan Fang, Jia-Le Cui, Shuyu Wang, Chenxing Liu-Sun, Xuezhao Wu, Zhihua Xiao, Bo Liu, Xin Si, Jun Yang, Qiming Shao, Hao Cai:
A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. 1-3 - Xingyu Qi, Yingzhe Sha, Xufeng Kou, Xiaoyong Xue, Peng Wang, Zhangcheng Huang, Qi Liu, Ming Liu:
A PMOS-Based Deep Cryogenic CMOS Temperature Sensor Achieving a Range from 10K to 410K with a Relative Inaccuracy of 0.5% (3σ). 1-3 - Yiming Han, Linran Zhao, Tzu-Ping Huang, Alper Bozkurt, Yaoyao Jia:
An 81.7M Ω-lnput-lmpedance 179.5dB-FOMSNDR 1.8Vpp-lnput-Range Noise-Shaping-SAR-Based Sensing Frontend with Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping-DEM. 1-3 - Yuanzhe Zhao, Yuheng Wang, Zijian Wang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang:
A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices. 1-3 - Heyang Zhao, Yuxuan He, Yunsong Tao, Zhishuai Zhang, Yong Chen, Yi Zhong, Lu Jie, Nan Sun:
A 0.16mm2450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques. 1-3 - Dingxuan Zhang, Tianrui Lyu, Jianping Guo:
An Up-to-70-V Output Hybrid Boost Converter with Halved Voltage Stress Achieving 7-W Output Power and 73.8% Peak Efficiency at CR of 14. 1-3 - Kent Edrian Lozada, Il-Hoon Jang, Ye-Dam Kim, Seung-Tak Ryu:
Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. 1-8 - Jinqiao Yang, Zikai Zhu, Longrun Xv, Anqin Xiao, Ziyi Yang, Lirong Zhenq, Zhuo Zou:
A 40nm 0.05-1.4uJ/inference Sample-Wise-Adaptive Spiking Neural Network Processor with Dynamic Neuron-Pruning and Unstructured-Model-Aware Architecture. 1-3 - Zihao Tang, Rui Paulo Martins, Mo Huang:
A Fast-transient Buck Converter with One-Cycle-Balancing Control for Single and Consecutive Load Steps. 1-3 - Gabriele Zanoletti, Gabriele Bè, Michele Rocco, Luca Ricci, Alessia Ceroni, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Andrea Bonfanti, Carlo Samori:
A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA. 1-3 - Linran Zhao, Yiming Han, Yaoyao Jia:
A 90.1dB SNDR, 180.2dB FoMSNDR, 10kHz BW Gm-C-based Δ Σ. ADC with Capacitive Input Feedforward and Duty-Cycled Gm Technique. 1-3 - Bo Wang, Amine Bermak, Man-Kay Law:
A 16-bit Incremental ADC Enabled by An Efficient Shooting Integrator with Inherent Noise Reduction. 1-3 - Jin Wang, Moxiao Lou, Zhengke Yang, Ruijie Peng, Humiao Li, Weirong Dong, Haoran Lyu, Yida Li, Jiamin Li, Hao Yu, Jerald Yoo, Longyang Lin:
A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers. 1-3 - Kaoru Yamashita, Kentaro Yoshioka, Christian Ziegler, Vadim Issakov, Hiroki Ishikuro:
A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique. 1-3 - Matthias Eberlein, Sebastian Ruping:
A 0.6V Supply Ultra-Compact Voltage Reference Exploiting MOS Threshold Correlations. 1-3 - Xinhang Xu, Yaohui Luan, Jie Li, Jihang Gao, Kwok Cheong Li, Jiajia Cui, Ru Huang, Linxiao Shen:
A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs. 1-3 - Neelkamal Semwal, Luigi Fassio, Massimo Alioto:
On-Chip Circuit Harness Enabling Probe-Less, Position-Invariant and Massive Testing of Chiplets via Die Front/Back-Side Capacitive Coupling. 1-3 - Haoyang Luo, Zongnan Wang, Jiarui Wang, Bingrui Li, Zilong Shen, Yang Liu, Xiaojie Duan, Yuan Wang, Xiyuan Tang:
A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator. 1-3 - Yiling Xie, Jianping Guo:
A 12V/24V-to-1V Shared Switched-Capacitor Multi-Inductor Multi-Output Converter with 90.9%/89.5%Peak Efficiency and Negligible Cross Regulation. 1-3 - Hyunjun Park, Yunho Lee, Minsu Kim, Woojoong Jung, Hongseok Kim, Hyung-Min Lee:
An Inductor-First Hybrid Buck-Boost Converter Featuring Seamless Single-Mode Operation, 97.2% Peak Efficiency, and 565mAlmm3 Current Density with Ultra-Compact 1 mm3-Volume Inductor. 1-3 - Wenbin Jia, Yifan He, Xiang Li, Yixuan Xie, Zongle Huang, Wenxun Wang, Boju Chen, Yaolei Li, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu:
Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks. 1-3 - Jun Chang, Hongzhi Liang, Yixiao Luo, Zeyu Peng, Zhe Li, Yi Shen, Shubin Liu, Zhangming Zhu:
A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter. 1-3 - Shousheng Han, Fei Song, Zhongyao Zhu, Xiaoming Wu, Hanjun Jiang, Tianling Ren, Yan Lu:
A LEGO-Like Easy-Stacking Step-Up SC Converter with Ultra-High and Wide VCR Using All Input-Stress-Only Devices. 1-3 - David-Peter Wiens, Ahmed Abdelaal, Bjoern Driemeyer, Joachim Becker, John G. Kauffman, Maurits Ortmanns:
A Direct Digitizing, 1MHz Bandwidth, 28fA/√Hz Current Sensing Front-End Based on a Mixed-Signal Integrator-Differentiator TIA in 28nm CMOS. 1-3 - Tianqi Lu, Xianglong Li, Wenyu Peng, Sijun Du:
A 0.49W 120.230VRMS to 8.12VDC Power Converter with Switched-Capacitor Regulation and Rectifier Short Flipping Achieving Maximized Bridge Conduction Time. 1-3 - Akiyoshi Tanaka, Shan He, Reza Mounesi, Xinjian Liu, Omar Faruqe, Nugaira Gahan Mim, Daniel S. Truesdell, Adel Nasiri, Benton H. Calhoun:
An 81.0% Peak Efficiency, 1.0W/cm3 Miniaturized 5V/1A AC-DC Converter Using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching. 1-3 - Neusha Javidnia, Bita Darvish Rouhani, Farinaz Koushanfar:
Key, Value, Compress: A Systematic Exploration of KV Cache Compression Techniques. 1-3 - Amirreza Shoobi, Alexander J. Geers, Anish Mondal, Kaisarbek Omirzakhov, Farshid Ashtiani, Firooz Aflatouni:
Integrated Photonic-electronic Deep Neural Networks: from Sub-nanosecond Image Classification to PVT-tolerant Activation Functions. 1-6 - Haoyu Bai, Ling Hao, Dong Wang, Keer Gao, Han Huang, Jiazheng Zhou, Jiaqi He, Junhua Liu, Huailin Liao:
A 0.9mm2 SDR Receiver in 40-nm CMOS Covering 10-72GHz Using Inductor-Less Based LO Quintupler. 1-3 - Ji Xiong, Yongling Zhang, Junzai Chen, Xiaoyu Li, Jinrui ZuO, Yan Wang, Xiaoyi Wang, Miao Meng:
A Wearable Backscatter System Featuring Concurrent RF Harvesting and Bidirectional Communication with Commodity BLE Transceivers. 1-3 - Luhua Lin, Bowen Wang, Longhao Kuang, Woogeun Rhee, Zhihua Wang:
A 1.8Gb/s 8GHz PSK-UWB Transceiver with Extended PPM/PWM Modulation and Embedded Carrier Spreading. 1-3 - Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw CH Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin:
A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited). 1-8 - Prashanth Mohan, Siddharth Das, Ken Mai:
A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET. 1-3 - Hongzhi Wu, Xuxu Cheng, Liping Zhong, Yangyi Zhang, Weitao Wu, Xiongshi Luo, Quan Pan:
A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. 1-3 - Hongzhi Liang, Jun Chang, Yixiao Luo, Zeyu Peng, Weimin Zhou, Li Dang, Yue Cao, Haolin Han, Yi Shen, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking. 1-3 - Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Wei-Chih Chen, Hsin-Hung Kuo, Shu-Chun Yang, Shenggao Li:
UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies. 1-8 - Ken Li, Wei-En Lee, Xitie Zhang, Tian Xie, Tzu-Han Wang, Visvesh Sathe, Shaolan Li:
A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer. 1-3 - Juyoung Oh, Jie-Xin Liu, Yi-Chen Teng, Hsueh-Cheng Wang, Dongsuk Jeon:
A 28-nm Real-Time Reinforcement Learning Processor for Mapless Autonomous Navigation with Unified Actor-Critic Network and Inference-on-Request Scheduling. 1-3 - Shih-Hao Chen, Ping-Sheng Wu, Brian Dean Soon, Chao-Hung Chen, Chun-Lung Hsu, Chih-Wei Liu, Chia-Hsiang Yang:
A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing. 1-3 - Yunbo Huang, Zunsong Yang, Hongyu Ren, Rui Paulo Martins, Yan Lu, Nan Sun, Nan Qi, Yong Chen:
A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. 1-3 - Jingshang Dong, Pei Qin, Haoshen Zhu, Xiang Yi, Wenjie Feng, Wenquan Che, Quan Xue:
An Ultra-Compact Wideband-Linearized Power Amplifier Achieving 0.24° AM-PM Distortion and Supporting 64-/256-/1024-/4096-QAM. 1-3 - Lingfeng Zhu, Chen Hu, Wing-Hung Ki, Xun Liu, Xiaosen Liu, Junmin Jiang:
A 6.87W 3.7-5V Input 12.6-24V Output Switched-Capacitor Sigma Converter with Multiple Voltage Domains. 1-3 - Yue Zhao, Pengda Qu, Guangshu Zhao, Feng Luo, Yang Jiang, Zhiming Xiao:
A 30V Step-Up Regulator with Shunt-Current-Reuse Controller for >85% Efficiency over 200µA-100mA Loading Range. 1-3 - Tianqi Lu, Sijun Du:
A 40.68MHz Dual-Output Wireless Power Transfer System Achieving 149.7mW Maximum Power and 90.3%/51.2% RX/E2E Efficiency with 8mm-Diameter RX Coil. 1-3 - Xiangdong Feng, Zhiyu Wang, Haoyang Li, Jiaqing Li, Guanglong Wu, Wei Wang, Weijin Lin, Xin Hu, Weixiao Wang, Zhong Tang, Yuyan Liu, Qinwen Fan, Hua Liu, Jianqiu Chen, Yuxuan Luo, Bo Zhao:
A Fully-Dynamic Capacitive Touch Sensor with Tri-Level Energy Recycling and Compressive Sensing Technique Achieving 1513 Hz Framerate and 10.66 pJ/Step Energy Efficiency. 1-3 - Chen Tang, Zongle Huang, Wenxun Wang, Yifan He, Shupei Fan, Xiaoyu Feng, Wenyu Sun, Yongpan Liu:
CCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation. 1-3 - Hanzhang Cao, Chuqiao Wang, Yanwei Liu, Wen Wu, Tongde Huang, Xiaolong Liu:
A 24.6-to-30.6GHz Magnetic-Isolated Sub-Sampling PLL with a Fast-Locking FLL Achieving 64.9fs Jitter, -253.3dB FoMJ, and -69.1dBc Reference Spur in 65nm CMOS. 1-3 - So-Yoon Yang, Deniz Umut Yildirim, Saransh Sharma, Donghyeon Han, Rishabh Mittal, Husna Ellis, Jaehong Jung, Eunseok Lee, Yubin Cai, Giovanni Traverso, Anantha P. Chandrakasan:
A Fully-Integrated Wireless Ingestible Drug Delivery Chip with Electrochemical Energy Harvesting and pH-Based MPPT. 1-3 - Yiwei Zou, Huan-Cheng Liao, Wei Wang, Wonjune Kim, Yumin Su, Jacob T. Robinson, Kaiyuan Yang:
A Parallel-Input Energy-Recycling Power Management Unit with Continuous MPPT for Magnetoelectrically Powered mm-Scale Bio-Implants. 1-3 - Hung-Yu Hou, Ya-Chen Tsai, Wei Foo, Yan-Ting Hsiao, Jun-Chau Chien:
A 0.7pArms Electrochemical Readout IC for Continuous Monitoring of Antibody Biologics in Upstream Biomanufacturing. 1-3 - Geoffrey W. Burr, H. Tsai, Irem Boybat, William Andrew Simon, Julian Büchel, Athanasios Vasilopoulos, Pritish Narayanan, Andrea Fasoli, Kohji Hosokawa, Manuel Le Gallo, M. Ishii, Yasuteru Kohda, Atsuya Okazaki, A. Chen, Charles Mackin, Elena Ferro, Kaoutar El Maghraoui, Hadjer Benmeziane, T. Philicelli, Corey Lammie, Alexander M. Friz, Jose Luquin, S. Jain, A. Sebastian, V. Narayanan:
Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited). 1-6 - Yingjie Zhu, Ruizhi Liu, Yiqing Lan, Yilong Dong, Zhenyu Guo, Ruohan Wu, Yuxin Chen, Longyang Lin, Jerald Yoo, Jiamin Li:
A Wireless Biopotential Sensing Node with Simultaneous Body-Channel Communication by TX-Coupled 21 Vpp Common-Mode Interference Suppression. 1-3 - Po-Han Chen, Zhiheng Luo, Spencer Chang, Kristopher Ngo, Ritwik Vatsyayan, Jihwan Lee, Tara Porter, Drew A. Hall, Shadi A. Dayeh, Ian Galton, Hanh-Phuc Le:
A Scalable 256-Channel 12-mA 0.06%-Current-Mismatch 22-V Neurostimulator with Real-Time Current Calibration and Compliance Monitoring. 1-3 - Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew:
A 2455μm2 1.7Gbps Side-Channel Attack-Resistant Masked HMAC-SHA256 Accelerator in Intel 4 CMOS. 1-3 - Yike Fang, Jie Zou, Xugang Ke, Lenian He:
A 96.1% Efficiency 48V-to-IBV GaN Power Converter with Full-Wave Temperature-Compensated Current Sensing and Adaptive Slope Emulation Achieving 4.3% Full-Temperature Sensing Error for AI Data Center Applications. 1-3 - Quan Cheng, Qiufeng Li, Weirong Dong, Mingtao Zhang, Ruilin Zhang, Mingqiang Huang, Hao Yu, Yiyu Shi, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto:
A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. 1-3 - Minhyeok Jeong, Hyungmin Gi, Minsik Cho, Mingyu Kim, Donggyu Kim, Sungyong Park, Woonjae Lee, Seonho Kim, Yeohoon Yoon, Shin Han, Donguk Seo, Jongmin Lee, Yoonmyung Lee:
A Phase-Locked Minimum-Energy-Point-Tracking Enabled by Unified-Clock-Power-and-Body-Bias Slack Regulation and PI-Ratio Based In-Situ Loop Gain Optimization with 97.4% Supply Voltage Margin Recovery at Minimum-Energy-Point in 28nm FDSOI. 1-3 - Yuke Shen, Shubin Liu, Deao Wu, Kui Wen, Yanbo Zhang, Yi Shen, Zhangming Zhu:
An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS. 1-3 - Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim:
A 1.8V Input, 96.5% Efficiency, 4.05A/mm2 FoM, Three-Level Dual-Path Hybrid Buck Converter with Mitigated Capacitive Inrush Current and Seamless DVS Across a Wide 0.4-to-1.5V Output Range. 1-3 - Hai Li, James S. Ayers, Anni Lu, You Li, Dmitri E. Nikonov, Yongping Fan, Ian A. Young:
16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization. 1-3 - Daxu Zhang, Dingxin Xu, Hongye Huang, Waleed Madany, Zezheng Liu, Wenqian Wang, Yuang Xiong, Ashbir Aviat Fadila, Duo Li, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada:
A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. 1-3 - Qin Chen, Xuhao Jiang, Xuanxuan Yang, Yuchen Liang, Ziang Zhang, Junbo Liu, Yifei Hu, Depeng Cheng, Long He, Xu Wu, Lianming Li:
A Compact Reconfigurable 24-29.5/38-43.5GHz Phased Array Transceiver Front-End with Self-Interference Rejection and Wideband IF Supporting TDD/FDD Operation. 1-3 - Bahram Jafari, Sankaran Aniruddhan, Shahriar Mirabbasi, Sudip Shekhar:
A 4.6-6GHz Self-Injection LC Oscillator Exploiting 2nd Harmonic Extraction and Self-Mixing to Achieve 5-35kHz 1/f3 Phase Noise Corner and 201dB FoMT. 1-3 - Xiaohua Huang, Dante G. Muratore:
Recording Front-End Electronics for Large-Scale Implantable Brain-Computer Interfaces: A Design Perspective. 1-8 - Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe:
A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. 1-3 - Yongqi Hu, Jue Huang, Chenkang Ning, Yumeng Yuan, Hao Xu, Na Yan, Xufeng Kou:
A Fractional-N Cascaded PLL Employing the Calibration-Free Noise-and-Spur Cancellation Technique. 1-3 - Yanchao Liu, Kaihang Wang, Yang Li, Yuchen Liu, Xiaohua Yu, Ronghua Ni:
A 37.5fs-rms Jitter and -254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset. 1-3 - Hangxiao Ma, Qiaobo Ma, Xuchu Mu, Yang Jiang, Rui Paulo Martins, Pui-In Mak:
A 30-110V Resonant Buck-Boost Power-Bus Charger Achieving 50-A Peak Laser-Current Pulse Generation in 2ns for MHz-Frequency Automotive LiDAR Transmitter. 1-3 - Omar Ismail, Paul Kaesser, Maurits Ortmanns:
Reducing the Impact of Non-Idealities on Incremental Δ∑ ADCs by Reconfiguration: A Review. 1-8 - Hang Wang, Hao Guo, Xiaohan Zhang, Taiyun Chi:
A Packaged D-Band Transmitter with a Multifeed Lens Antenna Achieving 25.3dBm Single-Element EIRP for 2-D Scalable Arrays. 1-3 - Aditya Wadaskar, Hesam Abbasi, Sreeni Poolakkal, Yen-Chin Wang, Benjamin W. Domae, Subhanshu Gupta, Danijela Cabric:
Demonstration of Fast OTA Chirp-Based Beam Training Using Analog TTD Array with Millimeter Wave Testbed for Applications in Radar Systems. 1-8 - Chang Liu, Burak Çatli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chua, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo-Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Alex Yang, Boyu Hu, Xin Meng, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao:
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm. 1-3 - Hyun-Seok Choi, Sunki Cho, Sanghee Lee, Hyeri Roh, Jeongeun Song, Honggyoo Ahn, Jihee Kim, Minchang Kim, Hankyu Chi, Deog-Kyoon Jeong, Woo-Seok Choi:
A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. 1-3 - Kathleen Feng, Kartik Prabhu, Kai Bartolone, Jeffrey Yu, Priyanka Raina:
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads. 1-3 - Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik:
A High-Performance Passive Base System for Distributed AI/Media Acceleration. 1-6 - Yudhajit Ray, Archisman Ghosh, Sarthak Antal, Shreyas Sen:
A 54μW Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion. 1-3 - Xin Zhao, Dengquan Li, Feida Wang, Depan Li, Yi Shen, Hongzhi Liang, Zhangming Zhu:
A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier. 1-3 - Po-Han Chen, Bo-Wun Cheng, Michael Oduoza, Zhouhua Xie, Kalhan Koul, Sai Gautham Ravipati, Yuchen Mei, Rupert Lu, Alex Carsello, Mark Horowitz, Priyanka Raina:
Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications. 1-3 - Qijing Xiao, Changgui Yang, Yunshan Zhang, Ziyi Chang, Cheng Chen, Xin Hu, Weixiao Wang, Guangjie Gu, Yuxuan Luo, Bo Zhao:
A Passive Crystal-Less Tag Demonstrating Battery-Free GSM-CW/5G-NR Downlink and BLE-to-BLE/BLE-to-WiFi/WiFi-to-WiFi Multi-Channel-Hopping Uplink with Smartphones. 1-3 - Yuanzhuo Wu, Rui Paulo Martins, Mo Huang:
A 300-kHz 3-Level Flyback Converter Achieving 93% Peak Efficiency and 50% Reduction in Transformer Size. 1-3 - Xinyuan Lin, Leran Huang, Chenhan Wei, Wenbin Jia, Hedi Wang, Wenxun Wang, Hongyang Jia, Huazhong Yang, Yongpan Liu:
A 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC. 1-3 - Amrith Sukumaran, Francesco Caruso, Régis Cattenoz, B. Putter, Jean-Luc Nagel, R. Ravanilla, I. Stergiou, G. Bouilly, P. Nussbaum, Stéphane Emery:
Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm2 Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation. 1-3 - Francesco Rezzi, V. Colonna, G. Gandolfi, Samuele Fusetto, M. Chiabrera, A. Savo, M. Costagliola, R. Stella, M. Bulzi, S. Radosav, D. Granozio, G. Alfieri, Alessandro Gemelli, Piero Malcovati, Edoardo Bonizzoni:
A 106.1dB DR, 450μA Idle Current Class-H Piezoelectric MEMS MicroSpeaker Driver with Envelope Tracking, Digital and Analog Inputs and Less Than 2.1μs Latency. 1-3 - Chenxi Han, Xiaoteng Zhao, Qi Zhang, Yuan Liu, Yuhao Zhang, Hongzhi Liang, Yukui Yu, Shubin Liu, Zhangming Zhu:
A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS. 1-3 - Lujie Peng, Xiben Jiao, Zhiyi Chen, Junyu Yang, Rui Hong, Longke Yan, Yu Long, Xiao Chen, Xiaoyu Miao, Zheng Wang, Zhengning Wang, Liang Zhou, Liang Chang, Shanshan Liu, Tae Hyoung Kim, Jun Zhou:
A High Accuracy and Ultra-Low Energy Environmental Sound Recognition Processor with Progressive Spectrogram Processing and Adaptive Weight Clustering Based Online Learning. 1-3 - Wenshuo Zhu, Xuan Sun, Xin Zhang, Cheng Huang:
A Multi-Level Power Management Architecture for Battery-Powered SPAD Drivers with Supply Intrinsic Quenching and 10-ns Dead Time. 1-3 - Xuwei Li, Depeng Cheng, Jing Feng, Xin Chen, Rui Cao, Lei Luo, Haipeng Duan, Dongming Wang, Lianming Li:
A 14.08 -Gb/s 256 -QAM 60 GHz Phased-Array Transceiver with Switchable Tertiary-Coil Transformer T/R Switch and Customizable-Sized Cascade Phase-Invariant VGAs. 1-3
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-16 00:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
