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ORCIDWoo-Rham Bae
Person information
- affiliation: Ayar Labs, Santa Clara, CA, USA
- affiliation: University of California Berkeley, Department of Electrical Engineering and Computer Sciences, CA, USA
- affiliation (PhD 2016): Seoul National University, South Korea
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Journal Articles
- 2022
[j24]Woorham Bae
:
Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures. IEEE Access 10: 80680-80694 (2022)- [j23]Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. IEEE J. Solid State Circuits 57(1): 140-152 (2022) - 2021
- [j22]Woo-Rham Bae:
Today's computing challenges: opportunities for computer hardware design. PeerJ Comput. Sci. 7: e420 (2021) - [j21]Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon:
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1012-1022 (2021) - 2020
- [j20]Woorham Bae, Kyung Jean Yoon:
Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal-Oxide-Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network-Based Stochastic Learning. Adv. Intell. Syst. 2(5): 2000011 (2020) - 2019
- [j19]Han-Gon Ko, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access 7: 38035-38043 (2019) - [j18]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits 54(7): 1993-2008 (2019) - [j17]Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019) - 2018
- [j16]Kwanseo Park, Woo-Rham Bae, Jinhyung Lee, Jeongho Hwang, Deog-Kyoon Jeong:
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS. IEEE J. Solid State Circuits 53(10): 2982-2993 (2018) - [j15]Jeongho Hwang, Gyu-Seob Jeong, Woo-Rham Bae, Jun-Eun Park, Chang-Soo Yoon, Jungmin Yoon, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(4): 436-440 (2018) - [j14]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong:
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j13]Woo-Rham Bae, Kyung Jean Yoon, Taeksang Song, Borivoje Nikolic:
A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1839-1843 (2018) - [j12]Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong:
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. 65(7): 5979-5989 (2018) - 2017
- [j11]Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong:
Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection. Sensors 17(9): 1962 (2017) - [j10]Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Woo-Rham Bae, Deog-Kyoon Jeong:
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1377-1381 (2017) - [j9]Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong:
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3543-3547 (2017) - 2016
- [j8]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. IEEE J. Solid State Circuits 51(10): 2312-2327 (2016) - [j7]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. IEEE J. Solid State Circuits 51(10): 2357-2367 (2016) - [j6]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1393-1403 (2016) - [j5]Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1106-1110 (2016) - [j4]Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong:
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2234-2243 (2016) - 2015
- [j3]Woo-Rham Bae, Deog-Kyoon Jeong:
A power-efficient 600-mVpp voltage-mode driver with independently matched pull-up and pull-down impedances. Int. J. Circuit Theory Appl. 43(12): 2057-2071 (2015) - [j2]Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - 2014
- [j1]Byoung-Joo Yoo, Woo-Rham Bae, Jiho Han, Jaeha Kim, Deog-Kyoon Jeong:
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1226-1237 (2014)
Conference and Workshop Papers
- 2021
- [c23]Woorham Bae:
State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey. ISCAS 2021: 1-5 - [c22]Colin Schmidt, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic:
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ISSCC 2021: 58-60 - [c21]Mark T. Wade, Erik Anderson, Shahab Ardalan, Woorham Bae, Behrooz Beheshtian, Sidney Buchbinder, Ken Chang, Paulo Chao, Haritha Eachempatti, John Frey, Eric Jan, Austin Katzin, Anatoly Khilo, Derek Kita, Uma Krishnamoorthy, Chen Li, Haiwei Lu, Fernando Luna, Christopher Madden, Lynne Okada, Mukundrai Patel, Chandru Ramamurthy, Manan Raval, Radek Roucka, Kit Robberson, Michael Rust, Derek Van Orden, Ron Zeng, Mason Zhang, Vladimir Stojanovic, Forrest Sedgwick, Roy Meade, Norman Chan, John Michael Fini, Byungchae Kim, Songtao Liu, Chong Zhang, Daniel Jeong, Pavan Bhargava, Matt Sysak, Chen Sun:
An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser. OFC 2021: 1-3 - [c20]Mark Wade, Daniel Jeong, Byungchae Kim, Mason Zhang, Woorham Bae, Chong Zhang, Pavan Bhargava, Derek Van Orden, Shahab Ardalan, Chandarasekaran Ramamurthy, Erik Anderson, Austin Katzin, Haiwei Lu, Sidney Buchbinder, Behrooz Beheshtian, Anatoly Khilo, Michael Rust, Chen Li, Forrest Sedgwick, John Michael Fini, Roy Meade, Vladimir Stojanovic, Chen Sun:
Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing. VLSI Circuits 2021: 1-2 - 2019
- [c19]Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon:
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC 2019: 1-4 - 2018
- [c18]Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic:
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC 2018: 285-288 - [c17]Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon:
BAG2: A process-portable framework for generator-based AMS circuit design. CICC 2018: 1-8 - [c16]Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic:
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC 2018: 322-325 - 2017
- [c15]Kwanseo Park, Woo-Rham Bae, Deog-Kyoon Jeong:
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control. CICC 2017: 1-4 - 2016
- [c14]Woo-Rham Bae, Haram Ju, Kwanseo Park, Deog-Kyoon Jeong:
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. A-SSCC 2016: 241-244 - [c13]Haram Ju, Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. ISCAS 2016: 2346-2349 - [c12]Woo-Rham Bae, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS. ISCAS 2016: 2906 - 2015
- [c11]Woo-Rham Bae, Haram Ju, Kwanseo Park, Sung-Yong Cho, Deog-Kyoon Jeong:
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. A-SSCC 2015: 1-4 - [c10]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - [c9]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong:
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387 - [c8]Woo-Rham Bae, Chang-Soo Yoon, Deog-Kyoon Jeong:
A low-power pulse position modulation transceiver. ISCAS 2015: 1614-1617 - [c7]Kwanseo Park, Woo-Rham Bae, Haram Ju, Jinhyung Lee, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. ISCAS 2015: 2389-2392 - 2014
- [c6]Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. A-SSCC 2014: 101-104 - [c5]Woo-Rham Bae, Deog-Kyoon Jeong, Byoung-Joo Yoo:
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. DDECS 2014: 55-58 - [c4]Woo-Rham Bae, Deog-Kyoon Jeong:
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth. ICEIC 2014: 1-2 - [c3]Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong:
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line. ESSCIRC 2014: 447-450 - [c2]Yoonsoo Kim, Woo-Rham Bae, Deog-Kyoon Jeong:
A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS. ISCAS 2014: 1869-1872 - 2012
- [c1]Woo-Rham Bae, Byoung-Joo Yoo, Deog-Kyoon Jeong:
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. ISOCC 2012: 49-52
Coauthor Index
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