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ORCIDKanak Agarwal 0001
Person information
- affiliation: Arm Research
- affiliation: IBM Research Division, Austin Research Lab, Austin, TX, USA
Other persons with the same name
- Kanak Agarwal 0002
![[0009-0003-9509-1557]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0009-0003-9509-1557")
— Manipal Institute of Technology, Department of Aeronautical and Automobile Engineering, India
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2020 – today
- 2020
[c61]Alexandre Ferreira, Eric Van Hensbergen, Chris Adeniyi-Jones, Edmund Grimley-Evans, Josh Minor, Mark Nutter, Luis E. Peña, Kanak Agarwal, Jon Hermes:
SMARTER: Experiences with Cloud Native on the Edge. HotEdge 2020
2010 – 2019
- 2016
- [j13]Ahmed Gheith, Ramakrishnan Rajamony, Patrick J. Bohrer, Kanak Agarwal, Michael Kistler, B. L. White Eagle, C. A. Hambridge, John B. Carter, T. Kaplinger:
IBM Bluemix Mobile Cloud Services. IBM J. Res. Dev. 60(2-3) (2016) - [c60]Keqiang He, Eric Rozner, Kanak Agarwal, Yu (Jason) Gu, Wes Felter, John B. Carter, Aditya Akella:
AC/DC TCP: Virtual Congestion Control Enforcement for Datacenter Networks. SIGCOMM 2016: 244-257 - 2015
- [c59]Raphael Robertazzi, Kanak Agarwal, Bucknell Webb, Christy Tyberg:
TSV/FET proximity study using dense addressable transistor arrays. IRPS 2015: 3 - [c58]Keqiang He, Eric Rozner, Kanak Agarwal, Wes Felter, John B. Carter, Aditya Akella:
Presto: Edge-based Load Balancing for Fast Datacenter Networks. SIGCOMM 2015: 465-478 - 2014
- [c57]Kanak Agarwal:
Wire-Speed Differential SOAP Encoding. ICWS 2014: 217-224 - [c56]Jeff Rasley, Brent E. Stephens, Colin Dixon, Eric Rozner, Wes Felter, Kanak Agarwal, John B. Carter, Rodrigo Fonseca:
Low-latency Network Monitoring via Oversubscribed Port Mirroring. ONS 2014 - [c55]Kanak Agarwal, Eric Rozner, Colin Dixon, John B. Carter:
SDN traceroute: tracing SDN forwarding without changing network behavior. HotSDN 2014: 145-150 - [c54]Kanak Agarwal, Colin Dixon, Eric Rozner, John B. Carter:
Shadow MACs: scalable label-switching for commodity ethernet. HotSDN 2014: 157-162 - [c53]Jeff Rasley, Brent E. Stephens, Colin Dixon, Eric Rozner, Wes Felter, Kanak Agarwal, John B. Carter, Rodrigo Fonseca:
Planck: millisecond-scale monitoring and control for commodity networks. SIGCOMM 2014: 407-418 - 2013
- [j12]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 202-215 (2013) - [c52]Kanak Agarwal, Raphael Polig:
A high-speed and large-scale dictionary matching engine for Information Extraction systems. ASAP 2013: 59-66 - 2012
- [c51]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Design-patterning co-optimization of SRAM robustness for double patterning lithography. ASP-DAC 2012: 713-718 - [c50]Kanak B. Agarwal, Shayak Banerjee:
Design driven patterning optimizations for low K1 lithography. ICICDT 2012: 1-4 - [c49]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta:
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. ICICDT 2012: 1-4 - [c48]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Design-aware lithography. ISPD 2012: 3-8 - 2011
- [c47]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif:
Electrically-driven retargeting for nanoscale layouts. CICC 2011: 1-4 - [c46]Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC 2011: 534-539 - [c45]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
A framework for double patterning-enabled design. ICCAD 2011: 14-20 - [c44]Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal:
REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. ICCAD 2011: 170-177 - [c43]Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif:
Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360 - [c42]Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky:
Coupling timing objectives with optical proximity correction for improved timing yield. ISQED 2011: 97-102 - [c41]Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Measuring within-die spatial variation profile through power supply current measurements. ISQED 2011: 711-715 - 2010
- [j11]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 722-736 (2010) - [j10]Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown:
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 166-170 (2010) - [c40]Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Analyzing electrical effects of RTA-driven local anneal temperature variation. ASP-DAC 2010: 739-744 - [c39]Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky:
Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. CICC 2010: 1-4 - [c38]Kanak Agarwal:
Frequency domain decomposition of layouts for double dipole lithography. DAC 2010: 404-407 - [c37]Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Closed-form modeling of layout-dependent mechanical stress. DAC 2010: 673-678 - [c36]Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky:
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE 2010: 1273-1278 - [c35]Kanak Agarwal:
On-die sensors for measuring process and environmental variations in integrated circuits. ACM Great Lakes Symposium on VLSI 2010: 147-150 - [c34]Vivek Joshi, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Analysis and optimization of SRAM robustness for double patterning lithography. ICCAD 2010: 25-31 - [c33]Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky:
SMATO: Simultaneous mask and target optimization for improving lithographic process window. ICCAD 2010: 100-106 - [c32]Cheng Zhuo, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Active learning framework for post-silicon variation extraction and test cost reduction. ICCAD 2010: 508-515 - [c31]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. ISQED 2010: 158-162 - [c30]Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic:
Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC 2010: 645-653
2000 – 2009
- 2009
- [c29]Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic:
Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD 2009: 418-424 - [c28]Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612 - 2008
- [j9]Dennis Sylvester, Kanak Agarwal, Saumil Shah:
Variability in nanometer CMOS: Impact, analysis, and minimization. Integr. 41(3): 319-339 (2008) - [j8]Kanak Agarwal, Sani R. Nassif:
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 86-97 (2008) - [c27]Kevin J. Nowka, Sani R. Nassif, Kanak Agarwal:
Characterization and design for variability and reliability. CICC 2008: 341-346 - [c26]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917 - [c25]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Stress aware layout optimization. ISPD 2008: 168-174 - [c24]Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic:
A Design Model for Random Process Variability. ISQED 2008: 734-737 - 2007
- [j7]Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 613-623 (2007) - [j6]Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka:
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1215-1224 (2007) - [c23]Kanak Agarwal, Sani R. Nassif:
Characterizing Process Variation in Nanometer CMOS. DAC 2007: 396-399 - [c22]Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka:
Rigorous extraction of process variations for 65nm CMOS design. ESSCIRC 2007: 89-92 - [c21]Kanak Agarwal, Frank Liu:
Efficient computation of current flow in signal wires for reliability analysis. ICCAD 2007: 741-746 - [c20]Kanak Agarwal, Kevin J. Nowka:
Dynamic Power Management by Combination of Dual Static Supply Voltages. ISQED 2007: 85-92 - 2006
- [j5]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 892-901 (2006) - [j4]Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical interconnect metrics for physical-design optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1273-1288 (2006) - [c19]Kanak Agarwal, Sani R. Nassif:
Statistical analysis of SRAM cell stability. DAC 2006: 57-62 - [c18]Emrah Acar, Kanak Agarwal, Sani R. Nassif:
Characterization of total chip leakage using inverse (reciprocal) gamma distribution. ISCAS 2006 - [c17]Sani R. Nassif, Kanak Agarwal, Emrah Acar:
Methods for estimating decoupling capacitance of nonswitching circuit blocks. ISCAS 2006 - [c16]Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester:
Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637 - 2005
- [c15]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan:
Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398 - [c14]Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506 - [c13]Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540 - [c12]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif:
Power-aware global signaling strategies. ISCAS (1) 2005: 604-607 - [c11]Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290 - 2004
- [j3]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 128-136 (2004) - [j2]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1346-1354 (2004) - [c10]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864 - [c9]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 - [c8]Saumil Shah, Kanak Agarwal, Dennis Sylvester:
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143 - [c7]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif:
Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193 - 2003
- [j1]Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu:
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 560-572 (2003) - [c6]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381 - [c5]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953 - [c4]Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264- - [c3]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses. SoC 2003: 97-100 - 2002
- [c2]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69 - [c1]Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC/VLSI Design 2002: 77-
Coauthor Index
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