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ORCIDStephen V. Kosonocky
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2020 – today
- 2023
[c28]Srikant Bharadwaj
, Shomit Das, Kaushik Mazumdar, Bradford M. Beckmann, Stephen Kosonocky:
Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUs. ASPLOS (4) 2023: 253-267- 2022
- [i1]Srikant Bharadwaj, Shomit Das, Kaushik Mazumdar, Bradford M. Beckmann, Stephen Kosonocky:
Predict; Do not React for Enabling Efficient Fine Grain DVFS in GPUs. CoRR abs/2205.00121 (2022) - 2021
- [c27]Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger:
A New Era of Tailored Computing. VLSI Circuits 2021: 1-2
2010 – 2019
- 2018
- [j12]Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak:
Zen: An Energy-Efficient High-Performance × 86 Core. IEEE J. Solid State Circuits 53(1): 102-114 (2018) - 2017
- [j11]Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy:
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits 52(1): 89-97 (2017) - [c26]Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co:
3.2 Zen: A next-generation high-performance ×86 core. ISSCC 2017: 52-53 - 2016
- [c25]Ravinder Rachala, Miguel Rodriguez, Stephen Kosonocky, Milos Trajkovic:
Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor. ISLPED 2016: 88-93 - [c24]Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger:
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ISSCC 2016: 74-75 - [c23]Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger:
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. VLSID 2016: 565-566 - 2015
- [j10]Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. IEEE J. Solid State Circuits 50(1): 4-9 (2015) - [j9]Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White:
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits 50(1): 24-34 (2015) - 2014
- [c22]Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox:
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. ISSCC 2014: 104-105 - 2012
- [c21]Kyle Craig, Yousef Shakhsheer, Sudhanshu Khanna, Saad Arrabi, John C. Lach, Benton H. Calhoun, Stephen Kosonocky:
A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs. ISLPED 2012: 167-172 - [c20]Stephen Kosonocky, Vladimir Stojanovic, Kees van Berkel, Ming-Yang Chao, Tobias Knoll, Joshua Friedrich:
Power/performance optimization of many-core processor SoCs. ISSCC 2012: 508-509 - 2011
- [j8]Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger:
An x86-64 Core in 32 nm SOI CMOS. IEEE J. Solid State Circuits 46(1): 162-172 (2011) - [c19]Stephen Kosonocky:
Practical power gating and dynamic voltage/frequency scaling. Hot Chips Symposium 2011: 1-62 - 2010
- [j7]Stephen V. Kosonocky:
Are you having fun yet? IEEE Des. Test Comput. 27(6): 80 (2010) - [c18]Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, Amy Novak, Sam Naffziger:
An x86-64 core implemented in 32nm SOI CMOS. ISSCC 2010: 106-107
2000 – 2009
- 2008
- [j6]Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43(4): 946-955 (2008) - [c17]Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky:
Keeping hot chips cool: are IC thermal problems hot air? DAC 2008: 634-635 - 2007
- [j5]Stephen V. Kosonocky, Kazuo Yano:
Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 42(4): 720-721 (2007) - [j4]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou:
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 586-590 (2007) - [c16]Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis:
Early Power-Aware Design & Validation: Myth or Reality? DAC 2007: 210-211 - [c15]Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan:
Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262 - [c14]Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan:
Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED 2007: 275-280 - 2005
- [j3]Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky:
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. Integr. 38(3): 491-504 (2005) - 2004
- [c13]Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky:
Characterization of logic circuit techniques for high leakage CMOS technologies. ACM Great Lakes Symposium on VLSI 2004: 230-235 - [c12]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz:
Experimental measurement of a novel power gating structure with intermediate power saving mode. ISLPED 2004: 20-25 - [c11]Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky:
A synchronous interface for SoCs with multiple clock domains. SoCC 2004: 173-174 - 2003
- [j2]Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47(2-3): 283-298 (2003) - [j1]Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier:
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. IBM J. Res. Dev. 47(5-6): 611-630 (2003) - [c10]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato:
Minimizing inductive noise in system-on-a-chip with multiple power gating structures. ESSCIRC 2003: 635-638 - [c9]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel:
Understanding and minimizing ground bounce during mode transition of power gating structures. ISLPED 2003: 22-25 - 2002
- [c8]Victor V. Zyuban, Stephen V. Kosonocky:
Low power integrated scan-retention mechanism. ISLPED 2002: 98-102 - [c7]Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky:
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. ISVLSI 2002: 7-14 - 2001
- [c6]Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD 2001: 400-405 - [c5]Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown:
Enchanced multi-threshold (MTCMOS) circuits using variable well bias. ISLPED 2001: 165-169 - [c4]W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi:
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266
1990 – 1999
- 1998
- [c3]Kemal Ebcioglu, Jason Fritts, Stephen Kosonocky, Michael Gschwind, Erik R. Altman, Krishnan Kailas, Terry Bright:
An eight-issue tree-VLIW processor for dynamic binary translation. ICCD 1998: 488-495 - [c2]Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz:
Designing a Testable System on a Chip. VTS 1998: 2-7 - 1995
- [c1]Stephen V. Kosonocky, Richard J. Mammone:
A continuous density neural tree network word spotting system. ICASSP 1995: 305-308
Coauthor Index
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