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2020 – today
- 2024
[j52]Weidong Xue, Xinwei Yu, Yisen Zhang, Xin Ming, Jian Fang, Junyan Ren:
A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation. Microelectron. J. 152: 106354 (2024)- [c157]Yuguo Xiang
, Yutong Zhao, Dayan Zhou, Danfeng Zhai, Junyan Ren, Fan Ye:
Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC. ISCAS 2024: 1-5 - 2023
- [j51]Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen, Junyan Ren, Shunli Ma:
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. 51(4): 1530-1547 (2023) - [j50]Xinwei Yu, Yan Wang, Fan Ye, Junyan Ren:
Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer. IEEE Trans. Biomed. Circuits Syst. 17(5): 1062-1073 (2023) - [j49]Xinwei Yu, Zhi Chen, Siqing Wu, Lulu Liu, Hao Chi, Fan Ye, Junyan Ren:
28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4742-4754 (2023) - [j48]Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma:
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 233-242 (2023) - [c156]Bingrong Lyu, Fan Ye, Junyan Ren:
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. ASICON 2023: 1-4 - [c155]Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. ASICON 2023: 1-4 - [c154]Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma:
A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. ASICON 2023: 1-4 - [c153]Siqing Wu, Xinwei Yu, Xingtao Zhu, Fan Ye, Junyan Ren:
A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. ASICON 2023: 1-4 - [c152]Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu:
A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. ASICON 2023: 1-4 - [c151]Yutong Zhao, Yuguo Xiang, Fan Ye, Junyan Ren:
A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement. ISCAS 2023: 1-5 - 2022
- [j47]Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. 50(2): 367-381 (2022) - [j46]Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. 50(6): 1834-1854 (2022) - [j45]Leming He, Weijiang Xu, Yan Wang, Jia Zhou, Junyan Ren:
Sensitivity - Bandwidth Optimization of PMUT with Acoustical Matching Using Finite Element Method. Sensors 22(6): 2307 (2022) - [j44]Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen:
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4944-4957 (2022) - [j43]Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren:
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 304-308 (2022) - [j42]Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma:
A 6.5-mm2 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak Psat and 42% PAE. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4268-4272 (2022) - [c150]Xinwei Yu, Fan Ye, Junyan Ren:
A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. APCCAS 2022: 1-4 - [c149]Yutong Zhao, Fan Ye, Junyan Ren:
A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. APCCAS 2022: 209-212 - [c148]Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma:
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS 2022: 560-564 - [c147]Zhiyang Zhang, Xi Wang, Junyan Ren, Shunli Ma:
A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS. ISCAS 2022: 2215-2219 - [c146]Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren:
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS 2022: 2655-2659 - [c145]Jingchao Lan, Yuxuan Zhang, Fan Ye, Junyan Ren:
A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration. MWSCAS 2022: 1-5 - [c144]Lulu Liu, Yimin Wu, Xinwei Yu, Fan Ye, Junyan Ren:
A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier. MWSCAS 2022: 1-4 - [c143]Wenhan Lu, Yimin Wu, Fan Ye, Junyan Ren:
A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems. MWSCAS 2022: 1-4 - [c142]Xi Wang, Zhiyang Zhang, Junyan Ren, Shunli Ma:
A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System. MWSCAS 2022: 1-5 - 2021
- [j41]Dong Wei, Xuan Ding, Hai Yu, Yen-Cheng Kuan, Qun Jane Gu, Zhiwei Xu, Shunli Ma, Junyan Ren:
Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting. IEEE Access 9: 11943-11953 (2021) - [j40]Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren:
A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System. IEEE Access 9: 74752-74762 (2021) - [j39]Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access 9: 77545-77554 (2021) - [j38]Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren:
A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET. IEEE Access 9: 169107-169121 (2021) - [j37]Xubo Wang, Leming He, You-Cao Ma, Wenjuan Liu, Weijiang Xu, Junyan Ren, Antoine Riaud, Jia Zhou:
Development of Broadband High-Frequency Piezoelectric Micromachined Ultrasonic Transducer Array. Sensors 21(5): 1823 (2021) - [j36]Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren:
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 641-654 (2021) - [j35]Shunli Ma, Tianxiang Wu, Jincheng Zhang, Junyan Ren:
A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. IEEE Trans. Ind. Electron. 68(6): 5271-5280 (2021) - [c141]Xu Chen, Junyan Ren, Shunli Ma:
A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS. ASICON 2021: 1-4 - [c140]Hao Chi, Jun Xu, Fan Ye, Junyan Ren:
A High Linearity and Low Noise Anti-Aliasing Filter for ADCs. ASICON 2021: 1-4 - [c139]Ziwei Li, Yutong Zhao, Guoyao Wu, Fan Ye, Junyan Ren:
A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE. ASICON 2021: 1-4 - [c138]Jingqi Wang, Fan Ye, Junyan Ren:
A Three-Stage Comparator with High Speed and Low Power. ASICON 2021: 1-4 - [c137]Xi Wang, Junyan Ren, Shunli Ma:
An 4th-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS. ASICON 2021: 1-4 - [c136]Guoyao Wu, Ziwei Li, Yutong Zhao, Fan Ye, Junyan Ren:
A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC. ASICON 2021: 1-4 - [c135]Zhiyang Zhang, Junyan Ren, Shunli Ma:
A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs. ASICON 2021: 1-4 - [c134]Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren:
A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet. ASICON 2021: 1-4 - [c133]Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma:
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC 2021: 1-3 - [c132]Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren:
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC 2021: 195-198 - [c131]Min Chen, Yutong Zhao, Nuo Xu, Fan Ye, Junyan Ren:
A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. ISCAS 2021: 1-4 - [c130]Wenbin He, Fan Ye, Junyan Ren:
An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. ISCAS 2021: 1-4 - [c129]Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren:
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. ISOCC 2021: 9-10 - [c128]Jingchao Lan, Yan Zheng, Yimin Wu, Min Chen, Fan Ye, Junyan Ren:
A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. ISOCC 2021: 129-130 - [c127]Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren:
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC 2021: 246-247 - [c126]Min Chen, Nuo Xu, Yutong Zhao, Fan Ye, Junyan Ren:
A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network. MWSCAS 2021: 125-128 - [c125]Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS 2021: 292-296 - [c124]Jingchao Lan, Yan Zheng, Yimin Wu, Fan Ye, Junyan Ren:
A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique. MWSCAS 2021: 949-953 - 2020
- [j34]Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao:
Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model. IEEE Access 8: 197287-197299 (2020) - [j33]Shunli Ma, Tianxiang Wu, Junyan Ren:
A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. IEEE Access 8: 219695-219708 (2020) - [c123]Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren:
A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. APCCAS 2020: 3-6 - [c122]Yimin Wu, Shuai Li, Longheng Luo, Fan Ye, Junyan Ren:
An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. APCCAS 2020: 7-10 - [c121]Ziwei Li, Wenbin He, Fan Ye, Junyan Ren:
A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. APCCAS 2020: 39-42 - [c120]Wenbin He, Ziwei Li, Fan Ye, Junyan Ren:
A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. APCCAS 2020: 82-85 - [c119]Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren:
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS 2020: 205-208 - [c118]Yan Zheng, Fan Ye, Junyan Ren:
A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET. ISCAS 2020: 1-4 - [c117]Wenbin He, Fan Ye, Junyan Ren:
A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC. MWSCAS 2020: 337-340 - [c116]Fan Ye, Junyan Ren:
A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. MWSCAS 2020: 746-749 - [c115]Jincheng Zhang, Lihe Nie, Shunli Ma, Junyan Ren:
A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. MWSCAS 2020: 802-805
2010 – 2019
- 2019
- [j32]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. 84: 59-66 (2019) - [j31]Wenjuan Liu, Leming He, Xubo Wang, Jia Zhou, Weijiang Xu, Nikolay Smagin, Malika Toubal, Hao Yu, Yuandong Gu, Jinghui Xu, Denis Remiens, Junyan Ren:
3D FEM Analysis of High-Frequency AlN-Based PMUT Arrays on Cavity SOI. Sensors 19(20): 4450 (2019) - [j30]Shunli Ma, Hao Yu, Qun Jane Gu, Junyan Ren:
A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 555-568 (2019) - [c114]Longheng Luo, Xingchen Shen, Jianguo Diao, Fan Ye, Junyan Ren:
A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. ASICON 2019: 1-4 - [c113]Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. ASICON 2019: 1-4 - [c112]Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren:
A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. ASICON 2019: 1-4 - [c111]Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren:
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON 2019: 1-4 - [c110]Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON 2019: 1-4 - [c109]Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. ASICON 2019: 1-4 - [c108]Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. ASICON 2019: 1-4 - [c107]Wenbin He, Fan Ye, Junyan Ren:
A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. ASICON 2019: 594-597 - [c106]Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC 2019: 189-192 - [c105]Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren:
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC 2019: 197-200 - [c104]Fan Ye, Shuai Li, Min Zhu, Zhekan Ni, Junyan Ren:
A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement. ISCAS 2019: 1-4 - [c103]Longheng Luo, Yimin Wu, Jipeng Wei, Fan Ye, Junyan Ren:
A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique. ISCAS 2019: 1-4 - [c102]Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren:
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS 2019: 1-4 - [c101]Shuai Li, Jianguo Diao, Yimin Wu, Fan Ye, Junyan Ren:
A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter. MWSCAS 2019: 109-112 - [c100]Yimin Wu, Jingchao Lan, Shuai Li, Fan Ye, Junyan Ren:
A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications. MWSCAS 2019: 141-144 - [c99]Dong Wei, Xuan Ding, Hai Yu, Bo Yu, Shunli Ma, Qun Jane Gu, Junyan Ren:
A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS. MWSCAS 2019: 299-302 - [c98]Longheng Luo, Shuai Li, Jipeng Wei, Yimin Wu, Fan Ye, Junyan Ren:
A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC. MWSCAS 2019: 766-769 - [c97]Jianguo Diao, Shuai Li, Yimin Wu, Fan Ye, Jun Xu, Junyan Ren:
Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications. MWSCAS 2019: 1171-1174 - 2018
- [j29]Yongzhen Chen, Fan Ye, Junyan Ren:
An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. 73: 52-58 (2018) - [j28]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1584-1588 (2018) - [j27]Shunli Ma, Ning Li, Junyan Ren:
A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1554-1564 (2018) - [c96]Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren:
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS 2018: 18-21 - [c95]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS 2018: 42-45 - [c94]Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren:
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS 2018: 1-5 - [c93]Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren:
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS 2018: 1-4 - [c92]Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren:
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS 2018: 1-4 - [c91]Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. ISCAS 2018: 1-5 - [c90]Zhiyuan Dai, Hang Hu, Yimin Wu, Fan Ye, Junyan Ren:
A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC. MWSCAS 2018: 101-104 - [c89]Longheng Luo, Yimin Wu, Jianguo Diao, Fan Ye, Junyan Ren:
Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems. MWSCAS 2018: 137-140 - [c88]Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren:
A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS 2018: 392-395 - 2017
- [j26]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins:
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c87]Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren:
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. ASICON 2017: 28-31 - [c86]Xiaoqing Chen, Fan Ye, Junyan Ren:
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. ASICON 2017: 32-35 - [c85]Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren:
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. ASICON 2017: 179-182 - [c84]Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren:
A stacked-packaged 16-channel ADC for ultrasound application. ASICON 2017: 245-248 - [c83]Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren:
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON 2017: 295-298 - [c82]Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye, Junyan Ren:
A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. ASICON 2017: 686-689 - [c81]Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren:
An input buffer for 12bit 2GS/s ADC. ASICON 2017: 750-753 - [c80]Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren:
A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON 2017: 754-757 - [c79]Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye, Junyan Ren:
A 12bit asynchronous SAR-incremental sub-range ADC. ASICON 2017: 835-838 - [c78]Shunli Ma, Jili Sheng, Ning Li, Junyan Ren:
A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. A-SSCC 2017: 321-324 - [c77]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS 2017: 1-4 - [c76]Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren:
An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS 2017: 811-814 - [c75]Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren:
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS 2017: 1009-1012 - 2016
- [c74]Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong:
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. A-SSCC 2016: 353-356 - [c73]Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong:
Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. A-SSCC 2016: 357-360 - 2015
- [j25]Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren:
A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express 12(5): 20141143 (2015) - [j24]Weiru Gu, Fan Ye, Junyan Ren:
Switch-back based on charge equalization switching technique for SAR ADC. IEICE Electron. Express 12(6): 20150036 (2015) - [j23]Yuan Su, Fan Ye, Junyan Ren:
A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. IEICE Electron. Express 12(11): 20150368 (2015) - [j22]Hanchao Zhou, Ning Zhu, Wei Li, Zibo Zhou, Ning Li, Junyan Ren:
A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication. IEICE Trans. Electron. 98-C(1): 16-27 (2015) - [j21]Jiasen Huang, Junyan Ren, Wei Li:
Greedy Approach Based Heuristics for Partitioning Sparse Matrices. IEICE Trans. Inf. Syst. 98-D(10): 1847-1851 (2015) - [j20]Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren:
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 721-725 (2015) - [c72]Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren:
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON 2015: 1-4 - [c71]Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren:
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON 2015: 1-4 - [c70]Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren:
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. ASICON 2015: 1-4 - [c69]Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye, Junyan Ren:
LVDS transmitter with optimized high power-efficiency 8: 1 MUX. ASICON 2015: 1-4 - [c68]Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON 2015: 1-4 - [c67]Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren:
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. ASICON 2015: 1-4 - [c66]Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren:
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON 2015: 1-4 - [c65]Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren:
A 100MS/s 5bit fully digital flash ADC with standard cells. ASICON 2015: 1-4 - [c64]Xuerong Zhou, Xiangyan Xue, Fan Ye, Junyan Ren:
I/Q imbalance estimation in OFDM systems. ASICON 2015: 1-4 - [c63]Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren:
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON 2015: 1-4 - [c62]Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139 - [c61]Jiasen Huang, Weina Lu, Junyan Ren:
Greedy approach based heuristics for partitioning SpMxV on FPGAs. FPL 2015: 1-2 - 2014
- [j19]Mingshuo Wang, Fan Ye, Wei Li, Junyan Ren:
A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. IEICE Electron. Express 11(2): 20130986 (2014) - [j18]Mingshuo Wang, Li Lin, Fan Ye, Junyan Ren:
A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding. IEICE Electron. Express 11(12): 20140371 (2014) - [j17]Wei Fei, Hao Yu, Haipeng Fu, Junyan Ren, Kiat Seng Yeo:
Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 699-711 (2014) - [c60]Jiasen Huang, Junyan Ren, Jun Xu, Yuanyuan Wang:
General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging. BioCAS 2014: 129-132 - [c59]Shunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren:
A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. ESSCIRC 2014: 187-190 - [c58]Jiasen Huang, Junyan Ren, Wenbo Yin, Lingli Wang:
No zero padded sparse matrix-vector multiplication on FPGAs. FPT 2014: 290-291 - [c57]Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren:
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS 2014: 2361-2364 - [c56]Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS 2014: 2365-2368 - [c55]Shunli Ma, Junyan Ren, Hao Yu:
An overview of new design techniques for high performance CMOS millimeter-wave circuits. ISIC 2014: 292-295 - 2013
- [j16]Kaichen Zhang, Wei Li, Ning Li, Junyan Ren:
A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications. IEICE Electron. Express 10(5): 20130016 (2013) - [j15]Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren:
A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express 10(24): 20130882 (2013) - [j14]Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo:
A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 37-50 (2013) - [j13]Wei Fei, Hao Yu, Yang Shang, Deyun Cai, Junyan Ren:
A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 60-II(3): 127-131 (2013) - [j12]Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren:
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2834-2844 (2013) - [j11]Liang Liu, Junyan Ren, Jun Zhou, Fan Ye:
Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System. Wirel. Pers. Commun. 71(2): 1095-1107 (2013) - [c54]Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren:
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON 2013: 1-4 - [c53]Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON 2013: 1-4 - [c52]Jiasen Huang, Hao Chen, Junyan Ren, Fan Ye:
A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. ASICON 2013: 1-4 - [c51]Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren:
Low-complexity synchronizer used in DC-OFDM UWB system. ASICON 2013: 1-4 - [c50]Bing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren:
Automatic gain control algorithm with high-speed and double closed-loop in UWB system. ASICON 2013: 1-4 - [c49]Wenqing Lu, Gerald E. Sobelman, Xiaofang Zhou, Junyan Ren:
FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture. ASICON 2013: 1-4 - [c48]Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren:
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. ASICON 2013: 1-4 - [c47]Yuwen Wang, Fan Ye, Junyan Ren:
A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. ASICON 2013: 1-4 - [c46]Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren:
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. ASICON 2013: 1-4 - [c45]Shunli Ma, Wei Fei, Hao Yu, Junyan Ren:
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. CICC 2013: 1-4 - [c44]Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren:
Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. MWSCAS 2013: 558-561 - [c43]Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren:
Power efficient SAR ADC with optimized settling technique. MWSCAS 2013: 1156-1159 - 2012
- [j10]Yangyang Niu, Wei Li, Ning Li, Junyan Ren:
A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor. IEICE Electron. Express 9(24): 1842-1848 (2012) - [j9]Xiaolong Wang, Fan Ye, Junyan Ren:
Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems". IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2795-2798 (2012) - [j8]Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He:
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. 17(1): 10:1-10:23 (2012) - [c42]Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren:
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS 2012: 128-131 - [c41]Shunli Ma, Changming Chen, Yiwen Zhang, Junyan Ren:
A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. APCCAS 2012: 232-235 - [c40]Deping Huang, Wei Li, Jin Zhou, Ning Li, Junyan Ren, Jinghong Chen:
A time-to-digital converter based AFC for wideband frequency synthesizer. ISCAS 2012: 1299-1302 - [c39]Long Cheng, Yu-Jing Lin, Fan Ye, Ning Li, Junyan Ren:
Output-dependent delay cancellation technique for high-accuracy current-steering DACs. ISCAS 2012: 2729-2732 - [c38]Mingshuo Wang, Tao Lin, Fan Ye, Ning Li, Junyan Ren:
A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC. MWSCAS 2012: 274-277 - [c37]Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren:
A digitally calibrated current-steering DAC with current-splitting array. MWSCAS 2012: 278-281 - [c36]Xiaolong Wang, Yuankun Xue, Liang Liu, Fan Ye, Junyan Ren:
Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems. MWSCAS 2012: 924-927 - [c35]Chixiao Chen, ShengChang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren:
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS 2012: 1100-1103 - [c34]Long Cheng, Yu-Jing Lin, Mingshuo Wang, Fan Ye, Ning Li, Junyan Ren:
A cancellation technique for output-dependent delay differences in high-accuracy DACs. MWSCAS 2012: 1104-1107 - 2011
- [j7]Ting Gao, Feng Zhou, Wei Li, Fei Lan, Ning Li, Junyan Ren:
A 6.2-9.5 GHz receiver for Wimedia MB-OFDM and China UWB standard. Sci. China Inf. Sci. 54(2): 407-418 (2011) - [j6]Yunfeng Chen, Jinhan Fan, Wei Li, Ning Li, Junyan Ren:
A current-mode RF transmitter for 6-9 GHz MB-OFDM UWB application. Sci. China Inf. Sci. 54(2): 419-428 (2011) - [j5]Ting Gao, Wei Li, Yunfeng Chen, Ning Li, Junyan Ren:
A 5.5mW 80-400MHz Gm-C low pass filter with a unique auto-tuning system. IEICE Electron. Express 8(13): 1034-1039 (2011) - [j4]Yunfeng Chen, Renliang Zheng, Haipeng Fu, Wei Li, Ning Li, Junyan Ren:
A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration. IEICE Trans. Electron. 94-C(10): 1706-1708 (2011) - [j3]Wenqing Lu, Shuang Zhao, Xiaofang Zhou, Junyan Ren, Gerald E. Sobelman:
Reconfigurable baseband processing architecture for communication. IET Comput. Digit. Tech. 5(1): 63-72 (2011) - [j2]Liang Liu, Junyan Ren, Xiaojing Ma, Fan Ye:
A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s. Wirel. Pers. Commun. 57(4): 695-705 (2011) - [c33]Peng Zhang, Fan Ye, Junyan Ren:
Class-AB CMOS buffer with floating class-AB control. ASICON 2011: 120-123 - [c32]Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren:
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON 2011: 492-495 - [c31]Chen Lian, Wei Li, Haipeng Fu, Ning Li, Junyan Ren:
Low phase noise injection-locked doubler-based quadrature CMOS VCO. ASICON 2011: 614-617 - [c30]Yuan Yao, Fan Ye, Junyan Ren:
Area efficient LDPC decoder design for parallel layered decoding. ASICON 2011: 679-682 - [c29]Haipeng Fu, Hanchao Zhou, Yangyang Niu, Junyan Ren, Wei Li, Ning Li:
A low-voltage differential injection locked divider with forward body bias. ASICON 2011: 731-734 - [c28]Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren:
A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. ASICON 2011: 894-897 - [c27]Qin Wu, Wei Li, Ning Li, Junyan Ren:
A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process. ASICON 2011: 978-981 - [c26]Ting Gao, Wei Li, Ning Li, Junyan Ren:
A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system. ASP-DAC 2011: 115-116 - [c25]Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo:
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. A-SSCC 2011: 141-144 - [c24]Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren:
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC 2011: 349-352 - [c23]Long Cheng, Fan Ye, Hai-Feng Yang, Ning Li, Jun Xu, Junyan Ren:
Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. ISCAS 2011: 5-8 - [c22]Jin Zhou, Wei Li, Deping Huang, Chen Lian, Ning Li, Junyan Ren:
A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio. ISCAS 2011: 1145-1148 - [c21]Haipeng Fu, Deyun Cai, Junyan Ren, Wei Li:
A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications. ISCAS 2011: 1544-1547 - 2010
- [j1]Liang Liu, Fan Ye, Xiaojing Ma, Tong Zhang, Junyan Ren:
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 701-705 (2010) - [c20]Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He:
QuickYield: an efficient global-search based parametric yield estimation with performance constraints. DAC 2010: 392-397 - [c19]Yunfeng Chen, Jinhan Fan, Wei Li, Ning Li, Junyan Ren:
A current-mode 6-9GHz UWB transmitter with output power flattening technique. ISCAS 2010: 329-332 - [c18]Deping Huang, Jin Zhou, Wei Li, Ning Li, Junyan Ren:
A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver. ISCAS 2010: 2071-2074 - [c17]Jun Zhou, Liang Liu, Fan Ye, Junyan Ren:
Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems. ISCAS 2010: 2135-2138 - [c16]Danfeng Chen, Haipeng Fu, Yunfeng Chen, Wei Li, Fan Ye, Ning Li, Junyan Ren:
A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. ISCAS 2010: 2139-2192 - [c15]Guanghua Shu, Fan Ye, Yao Guo, Mingjun Fan, Junyan Ren, Jun Xu, Ning Li, Cheng Chen:
A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing. ISCAS 2010: 3016-3019
2000 – 2009
- 2009
- [c14]Lei Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren:
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. ESSCIRC 2009: 472-475 - [c13]Mingjun Fan, Junyan Ren, Yao Guo, Yuanwen Li, Fan Ye, Ning Li:
A Novel Operational Amplifier for Low-voltage Low-power SC Circuits. ISCAS 2009: 2289-2292 - [c12]Xi Gou, Yi-ran Li, Jian-qiu Chen, Jun Xu, Junyan Ren:
A Low Power Low Voltage 16 Bit Audio SigmaDelta Modulator. ISCAS 2009: 3142-3145 - [c11]Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren:
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. SoCC 2009: 39-42 - 2008
- [c10]Liang Liu, Xiaojing Ma, Fan Ye, Junyan Ren:
Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems. ICC 2008: 742-745 - 2007
- [c9]Zhujin Zhou, Ning Li, Wei Li, Junyan Ren:
A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers. ISCAS 2007: 437-440 - [c8]Lei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu:
A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch. ISCAS 2007: 1721-1724 - [c7]Zhuo Xu, Junyan Ren, Xuejing Wang, Fan Ye:
Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. ISCAS 2007: 2574-2577 - [c6]Liang Liu, Junyan Ren, Xuejing Wang, Fan Ye:
Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. ISCAS 2007: 2594-2597 - [c5]Xuejing Wang, Liang Liu, Fan Ye, Junyan Ren, Bo Hu:
A Novel Synchronizer for OFDM-based UWB System on New Preamble Design. PIMRC 2007: 1-5 - 2006
- [c4]Fangqing Chu, Wei Li, Junyan Ren:
An implementation of a CMOS down-conversion mixer for GSM1900 receiver. ASP-DAC 2006: 100-101 - [c3]Lu Ping, Ye Fan, Junyan Ren:
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet. ISCAS 2006 - 2003
- [c2]Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren:
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. ASP-DAC 2003: 885-890 - 2002
- [c1]Omar Wing, Tan Jun, Jinmei Lai, Junyan Ren, Qianling Zhang:
Iterative solution of ODE-PDE-AE systems for RF circuit simulation. ISCAS (4) 2002: 317-320
Coauthor Index
[c157] [j50] [j49] [c156] [c153] [c151] [j44] [j43] [c150] [c149] [c146] [c145] [c144] [c143] [j39] [j38] [j36] [c140] [c139] [c138] [c136] [c134] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [c116] [j32] [c114] [c110] [c109] [c107] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c98] [c97] [j29] [j28] [c96] [c95] [c94] [c93] [c92] [c91] [c90] [c89] [c88] [j26] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [c80] [c79] [c77] [c76] [c75] [j25] [j24] [j23] [j20] [c72] [c71] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [j19] [j18] [c57] [c56] [j15] [j12] [j11] [c54] [c53] [c52] [c51] [c50] [c48] [c47] [c43] [j9] [c42] [c39] [c38] [c37] [c36] [c35] [c34] [j2] [c33] [c32] [c30] [c28] [c24] [c23] [j1] [c17] [c16] [c15] [c14] [c13] [c11] [c10] [c7] [c6] [c5] [c3]
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