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2020 – today
- 2024
[j22]Virendra Singh
, Mahendra Pratap Singh, Saumya Hegde, Maanak Gupta:
Security in 5G Network Slices: Concerns and Opportunities. IEEE Access 12: 52727-52743 (2024)- [j21]Aditi Gupta, Sukanya Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh:
A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. Clust. Comput. 27(4): 4063-4076 (2024) - [j20]Sarath Babu, Virendra Singh:
BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier. Comput. Secur. 146: 104031 (2024) - [j19]Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh, Adnan M. Abu-Mahfouz:
DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. Pattern Recognit. Lett. 182: 125-132 (2024) - [c138]Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS 2024: 104-109 - [c137]Chandramani Chaudhary, Nirmal Kumar Boran, N. Sangeeth, Virendra Singh:
GNNDLD: Graph Neural Network with Directional Label Distribution. ICAART (2) 2024: 165-176 - [c136]Prakhar Diwan, Suryakant Toraskar, Varun Venkitaraman, Nirmal Kumar Boran, Chandramani Chaudhary, Virendra Singh:
MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. VLSID 2024: 348-353 - [c135]Raj Kumar Choudhary, Janeel Patel, Virendra Singh:
Early Execution for Soft Error Detection. VLSID 2024: 366-371 - 2023
- [c134]Gowthami Konganapalle, Sonali Shukla, Virendra Singh:
SMASh: A State Encoding Methodology Against Attacks on Finite State Machines. ATS 2023: 1-6 - [c133]Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh:
On Attacking Scan-based Logic Locking Schemes. DFT 2023: 1-4 - [c132]Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT 2023: 1-6 - [c131]Tikaram Sanyashi, Nirmal Kumar Boran, Virendra Singh:
Secure KNN Computation on Cloud. ICISS 2023: 197-216 - [c130]Raj Kumar Choudhary, Janeel Patel, Virendra Singh:
ERrOR: Improving Performance and Fault Tolerance Using Early Execution. IOLTS 2023: 1-3 - [c129]Prokash Ghosh, Yogesh Gholap, Virendra Singh:
On-Chip SRAM Disclosure Attack Prevention Technique for SoC. IOLTS 2023: 1-7 - [c128]Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS 2023: 1-7 - [c127]Pooja Choudhary, Lava Bhargava, G. U. Vinod, Ashok Kumar Suhag, Masahiro Fujita, Virendra Singh:
Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. iSES 2023: 115-120 - [c126]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh:
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. LATS 2023: 1-2 - [c125]Sonali Shukla, Bhavika Ranjeet Kumar, Virendra Singh:
SSSN: Secured Streaming Scan Network. LATS 2023: 1-6 - [c124]Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh:
TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. SOSE 2023: 91-97 - 2022
- [j18]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh, Ashok Kumar Suhag:
Approximating Arithmetic Circuits for IoT Devices Data Processing. Comput. Ind. Eng. 174: 108792 (2022) - [c123]Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI 2022: 394-397 - [c122]Nirmal Kumar Boran, Pranil Joshi, Virendra Singh:
PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. SECRYPT 2022: 443-450 - [c121]Anishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh:
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT 2022: 397-407 - [c120]Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh:
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. VDAT 2022: 435-449 - [c119]Ashwin Sanjay Lele, Srivatsava Jandhyala, Saurabh Gangurde, Virendra Singh, Sreenivas Subramoney, Udayan Ganguly:
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. VDAT 2022: 499-512 - [c118]Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda:
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. VTS 2022: 1-7 - 2021
- [j17]Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, Virendra Singh:
Fine-Grained Scheduling in Heterogeneous-ISA Architectures. IEEE Comput. Archit. Lett. 20(1): 9-12 (2021) - [j16]Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh:
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. IEEE Comput. Archit. Lett. 20(1): 62-65 (2021) - [j15]Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh:
A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. 37(5): 593-611 (2021) - [j14]V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh:
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 985-998 (2021) - [c117]Insha Amin, Deepak Mishra, Ravikant Saini, Virendra Singh:
Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay. ANTS 2021: 1-6 - [c116]Abhinish Anand, Winnie Thomas, Suryakant Toraskar, Virendra Singh:
Predictive Warp Scheduling for Efficient Execution in GPGPU. ACM Great Lakes Symposium on VLSI 2021: 295-300 - [c115]Winnie Thomas, Suryakant Toraskar, Virendra Singh:
Dynamic Optimizations in GPU Using Roofline Model. ISCAS 2021: 1-5 - [c114]Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh:
Enhancing Testbench Quality via Genetic Algorithm. MWSCAS 2021: 652-656 - [i1]Vedant Satav, Virendra Singh:
Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter. CoRR abs/2111.12281 (2021) - 2020
- [j13]Newton, Virendra Singh, Trevor E. Carlson:
PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures. IEEE Comput. Archit. Lett. 19(2): 151-154 (2020) - [j12]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 248-261 (2020) - [j11]Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1002-1015 (2020) - [c113]Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
LUT-based Circuit Approximation with Targeted Error Guarantees. ATS 2020: 1-6 - [c112]Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney:
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS 2020: 121-122 - [c111]Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSID 2020: 101-106
2010 – 2019
- 2019
- [j10]Binod Kumar, Masahiro Fujita, Virendra Singh:
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. 35(5): 655-678 (2019) - [j9]Shoba Gopalakrishnan, Virendra Singh:
Soft-error reliable architecture for future microprocessors. IET Comput. Digit. Tech. 13(3): 233-242 (2019) - [c110]Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh:
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS 2019: 99-104 - [c109]Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh:
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS 2019: 123-128 - [c108]Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh:
Preventing Scan Attack through Test Response Encryption. DFT 2019: 1-6 - [c107]Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat, Virendra Singh:
Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. ICCD 2019: 702-705 - [c106]Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
Securing Scan through Plain-text Restriction. IOLTS 2019: 251-252 - [c105]Antara Ganguly, Rajeev Muralidhar, Virendra Singh:
Towards Energy Efficient non-von Neumann Architectures for Deep Learning. ISQED 2019: 335-342 - [c104]Jaidev Shenoy, Kelly Ockunzzi, Virendra Singh, Kushal Kamal:
On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. VLSID 2019: 106-111 - [c103]Binod Kumar, Masahiro Fujita, Virendra Singh:
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSID 2019: 389-394 - [e7]Sukumar Nandi, Devesh Jinwala, Virendra Singh, Vijay Laxmi, Manoj Singh Gaur, Parvez Faruki:
Security and Privacy - Second ISEA International Conference, ISEA-ISAP 2018, Jaipur, India, January, 9-11, 2019, Revised Selected Papers. Communications in Computer and Information Science 939, Springer 2019, ISBN 978-981-13-7560-6 [contents] - [e6]S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh:
VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers. Communications in Computer and Information Science 892, Springer 2019, ISBN 978-981-13-5949-1 [contents] - [e5]Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1 [contents] - 2018
- [j8]Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh:
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34(1): 53-65 (2018) - [c102]Rohini Gulve, Virendra Singh:
ATPG power guards: On limiting the test power below threshold. DATE 2018: 301-304 - [c101]Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh:
Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. EWDTS 2018: 1-6 - [c100]Suhit Pai, Newton Singh, Virendra Singh:
AB-Aware: Application Behavior Aware Management of Shared Last Level Caches. ACM Great Lakes Symposium on VLSI 2018: 237-242 - [c99]Binod Kumar, Kanad Basu, Virendra Singh:
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC 2018: 1-8 - [c98]Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta:
A PAM-4 10S/12S line coding scheme with equi-probable levels. ISCAS 2018: 1-5 - [c97]Nihar Hage, Satyadev Ahlawat, Virendra Singh:
In-situ Monitoring for Slack Time Violation Without Performance Penalty. ISCAS 2018: 1-5 - [c96]Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh:
On Securing Scan Design Through Test Vector Encryption. ISCAS 2018: 1-5 - [c95]Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh:
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI 2018: 46-51 - [c94]Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita:
Memory-system requirements for convolutional neural networks. MEMSYS 2018: 291-197 - 2017
- [j7]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33(6): 721-739 (2017) - [c93]Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh:
On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS 2017: 58-63 - [c92]Satyadev Ahlawat, Darshit Vaghani, Virendra Singh:
Preventing scan-based side-channel attacks through key masking. DFT 2017: 1-4 - [c91]Shoba Gopalakrishnan, Virendra Singh:
REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. DFT 2017: 1-6 - [c90]Satyadev Ahlawat, Darshit Vaghani, Virendra Singh:
An efficient test technique to prevent scan-based side-channel attacks. ETS 2017: 1-2 - [c89]Rohini Gulve, Anshu Goel, Virendra Singh:
PHP: Power hungry pattern generation at higher abstraction level. EWDTS 2017: 1-4 - [c88]V. S. Vineesh, Nihar Hage, B. Karthik, Virendra Singh:
Achieving full functional coverage for the forwarding unit of pipelined processors. EWDTS 2017: 1-4 - [c87]Abhishek Rajgadia, Newton, Virendra Singh:
EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. ACM Great Lakes Symposium on VLSI 2017: 113-118 - [c86]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI 2017: 191-196 - [c85]Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT 2017: 59-66 - [c84]Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh:
DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. ICCD 2017: 345-352 - [c83]Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh:
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS 2017: 132-137 - [c82]Toral Shah, Anzhela Yu. Matrosova, Virendra Singh:
Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS 2017: 211-212 - [c81]Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
Instruction-based self-test for delay faults maximizing operating temperature. IOLTS 2017: 259-264 - [c80]Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh:
A low cost technique for scan chain diagnosis. ISCAS 2017: 1-4 - [c79]Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja:
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC 2017: 1-10 - [c78]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. LATS 2017: 1-6 - [c77]Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh:
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS 2017: 1-6 - [c76]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
Identifying high variability speed-limiting paths under aging. LATS 2017: 1-6 - [c75]Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC 2017: 1-6 - [c74]Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID 2017: 147-152 - [c73]Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh:
On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSID 2017: 397-402 - [e4]Rudrapatna K. Shyamasundar, Virendra Singh, Jaideep Vaidya:
Information Systems Security - 13th International Conference, ICISS 2017, Mumbai, India, December 16-20, 2017, Proceedings. Lecture Notes in Computer Science 10717, Springer 2017, ISBN 978-3-319-72597-0 [contents] - [e3]Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh:
VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Communications in Computer and Information Science 711, Springer 2017, ISBN 978-981-10-7469-1 [contents] - 2016
- [c72]Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh:
Enabling LOS delay test with slow scan enable. EWDTS 2016: 1-4 - [c71]Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh:
Performance modelling of heterogeneous ISA multicore architectures. EWDTS 2016: 1-4 - [c70]Rohini Gulve, Virendra Singh:
ILP based don't care bits filling technique for reducing capture power. EWDTS 2016: 1-4 - [c69]Binod Kumar, Ankit Jindal, Virendra Singh:
A trace signal selection algorithm for improved post-silicon debug. EWDTS 2016: 1-4 - [c68]Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu:
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS 2016: 1-4 - [c67]Toral Shah, Virendra Singh, Anzhela Yu. Matrosova:
ROBDD based path delay fault testable combinational circuit synthesis. EWDTS 2016: 1-4 - [c66]Shoba Gopalakrishnan, Virendra Singh:
REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. IOLTS 2016: 109-114 - [c65]Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh:
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS 2016: 233-238 - 2015
- [c64]Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh:
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS 2015: 25-30 - [c63]Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS 2015: 115-120 - [c62]Adithyalal P. M, Shankar Balachandran, Virendra Singh:
A Soft Error Resilient Low Leakage SRAM Cell Design. ATS 2015: 133-138 - [c61]Parth Lathigara, Shankar Balachandran, Virendra Singh:
Application behavior aware re-reference interval prediction for shared LLC. ICCD 2015: 172-179 - [c60]Toral Shah, Anzhela Yu. Matrosova, Virendra Singh:
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT 2015: 1-2 - 2014
- [j6]Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson:
Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems. Microelectron. Reliab. 54(5): 1022-1049 (2014) - [c59]Nahit Pawar, Madhu N. Belur, Mani Bhushan, A. P. Tiwari, M. G. Kelkar, M. Pramanik, Virendra Singh:
A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors. EAIS 2014: 1-7 - [c58]Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh:
Partially programmable circuit design. EWDTS 2014: 1-4 - [c57]Indira Rawat, M. K. Gupta, Virendra Singh:
Temperature aware test scheduling by modified floorplanning. EWDTS 2014: 1-4 - [c56]Lokesh Siddhu, Amit Mishra, Virendra Singh:
Operand Isolation with Reduced Overhead for Low Power Datapath Design. VLSID 2014: 483-488 - 2013
- [j5]Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh:
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. 74(7): 1164-1177 (2013) - [c55]Indira Rawat, M. K. Gupta, Virendra Singh:
Thermal analysis and modeling of 3D integrated circuits for test scheduling. 3DIC 2013: 1-5 - [c54]Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Virendra Singh:
Delay testable sequential circuit designs. EWDTS 2013: 1-4 - [c53]Anzhela Yu. Matrosova, Ekaterina Nikolaeva, Dmitry Kudin, Virendra Singh:
PDF testability of the circuits derived by special covering ROBDDs with gates. EWDTS 2013: 1-5 - [c52]Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh:
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS 2013: 1-6 - [c51]Indira Rawat, M. K. Gupta, Virendra Singh:
Scheduling tests for 3D SoCs with temperature constraints. EWDTS 2013: 1-4 - [c50]Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP. VDAT 2013: 345-352 - [c49]Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal:
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013 - [e2]Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh:
VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers. Communications in Computer and Information Science 382, Springer 2013, ISBN 978-3-642-42023-8 [contents] - 2012
- [j4]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. 28(4): 541-549 (2012) - [j3]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. 28(5): 757-771 (2012) - [c48]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU tolerant robust memory cell design. IOLTS 2012: 13-18 - [c47]Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh:
Impact of process variations on computers used for image processing. ISCAS 2012: 1444-1447 - [c46]Pawan Kumar, Virendra Singh:
Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. SIN 2012: 103-110 - [c45]Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. VDAT 2012: 172-179 - [c44]Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU Tolerant Robust Latch Design. VDAT 2012: 223-232 - [c43]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Derating based hardware optimizations in soft error tolerant designs. VTS 2012: 282-287 - [e1]Manoj Singh Gaur, Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Virendra Singh:
5th International Conference of Security of Information and Networks, SIN '12, Jaipur, India, October 22 - 26, 2012. ACM 2012, ISBN 978-1-4503-1668-2 [contents] - 2011
- [c42]Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh:
SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium 2011: 60-65 - [c41]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376 - [c40]Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh:
GA Based Congestion Aware Topology Generation for Application Specific NoC. DELTA 2011: 93-98 - [c39]Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson:
Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. DSN Workshops 2011: 59-64 - [c38]Anzhela Yu. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh:
Selection of the state variables for partial enhanced scan techniques. EWDTS 2011: 285-290 - [c37]Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh:
Parallelizing TUNAMI-N1 Using GPGPU. HPCC 2011: 845-850 - [c36]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD 2011: 419-426 - [c35]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Reduced overhead soft error mitigation using error control coding techniques. IOLTS 2011: 163-168 - [c34]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM cell. ISQED 2011: 597-602 - [c33]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Testing linear and non-linear analog circuits using moment generating functions. LATW 2011: 1-6 - [c32]Virendra Singh, Masahiro Fujita:
Tutorial: "Post silicon debug of SOC designs". SoCC 2011: 18 - [c31]Manas Kumar Puthal, Virendra Singh, Manoj Singh Gaur, Vijay Laxmi:
C-Routing: An adaptive hierarchical NoC routing methodology. VLSI-SoC 2011: 392-397 - [c30]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69 - 2010
- [c29]Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh:
Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium 2010: 367-370 - [c28]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE 2010: 1572-1577 - [c27]Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson:
Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. DELTA 2010: 281-285 - [c26]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN 2010: 121-130 - [c25]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Modified T-Flip-Flop based scan cell for RAS. ETS 2010: 113-118 - [c24]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. ETS 2010: 259 - [c23]Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh:
Path delay faults and ENF. EWDTS 2010: 164-167 - [c22]Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh:
On selection of state variables for delay test of identical functional units. EWDTS 2010: 200-203 - [c21]Viney Kumar, Rahul Raj Choudhary, Virendra Singh:
FREP: A soft error resilient pipelined RISC architecture. EWDTS 2010: 330-333 - [c20]N. S. Vinay, Indira Rawat, Erik Larsson, Manoj Singh Gaur, Virendra Singh:
Thermal aware test scheduling for stacked multi-chip-modules. EWDTS 2010: 343-349 - [c19]K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur:
Fault grading using Instruction-Execution graph. EWDTS 2010: 350-357 - [c18]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM for FPGA applications. FPT 2010: 491-494 - [c17]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara:
Graph theoretic approach for scan cell reordering to minimize peak shift power. ACM Great Lakes Symposium on VLSI 2010: 73-78 - [c16]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI 2010: 143-146 - [c15]V. Prasanth, Virendra Singh, Rubin A. Parekhji:
Robust detection of soft errors using delayed capture methodology. IOLTS 2010: 277-282 - [c14]A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Test application time minimization for RAS using basis optimization of column decoder. ISCAS 2010: 2614-2617 - [c13]Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh:
Genetic algorithm based topology generation for application specific Network-on-Chip. ISCAS 2010: 3156-3159 - [c12]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293 - [c11]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398
2000 – 2009
- 2009
- [c10]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68 - [c9]K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh:
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium 2009: 237-240 - [c8]Mikael Väyrynen, Virendra Singh, Erik Larsson:
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. DATE 2009: 484-489 - [c7]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal:
On Minimization of Peak Power for Scan Circuit during Test. ETS 2009: 25-30 - [c6]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74 - [c5]Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja:
DX-compactor: distributed X-compaction for SoCs. ACM Great Lakes Symposium on VLSI 2009: 505-510 - 2006
- [j2]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1203-1215 (2006) - 2005
- [j1]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode. IEICE Trans. Inf. Syst. 88-D(3): 610-618 (2005) - [c4]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750 - [c3]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689 - 2004
- [c2]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933- - 2003
- [c1]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71
Coauthor Index
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