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2020 – today
- 2024
[c131]Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon:
Secure eFPGA Configuration: A System-Level Approach. ARC 2024: 151-165- [c130]Seyed Mohammad Ali Zeinolabedin, Matthieu Couriol, Pierre-Emmanuel Gaillardon:
Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. MWSCAS 2024: 651-655 - [i9]Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace:
AIvril: AI-Driven RTL Generation With Verification In-The-Loop. CoRR abs/2409.11411 (2024) - 2023
- [j41]Walter Lau Neto
, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1912-1925 (2023) - [j40]Aurélien Alacchi, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon:
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2028-2036 (2023) - [j39]Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John:
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. ACM Trans. Reconfigurable Technol. Syst. 16(3): 50:1-50:34 (2023) - [j38]Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1128-1139 (2023) - [j37]Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon:
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1204-1213 (2023) - [j36]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1459-1471 (2023) - [c129]Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon:
Open-source and FPGAs: Hardware, Software, Both or None? FPGA 2023: 149 - [c128]Grant Brown, Ganesh Gore, Pierre-Emmanuel Gaillardon:
Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs. ISVLSI 2023: 1-6 - [i8]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [j35]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5126-5130 (2022) - [j34]Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
Programmable Local Clock SET Filtering for SEE-Resistant FPGA. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3879-3883 (2022) - [c127]Thomas Becnel, Kerry Kelly, Pierre-Emmanuel Gaillardon:
Tiny Time-Series Transformers: Realtime Multi-Target Sensor Inference At The Edge. COINS 2022: 1-6 - [c126]Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. DAC 2022: 421-426 - [c125]Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ALICE: an automatic design flow for eFPGA redaction. DAC 2022: 781-786 - [c124]Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
Programmable logic elements using multigate ambipolar transistors. DDECS 2022: 112-117 - [c123]Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. ISCAS 2022: 273-277 - [c122]Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon:
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. VLSI-SoC 2022: 1-6 - [d1]Thomas Becnel, Kerry Kelly, Pierre-Emmanuel Gaillardon:
University of Utah AirU Pollution Monitoring Network - Salt Lake City UT - 2019-07-26 - 2021-05-14. IEEE DataPort, 2022
- [i7]Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. CoRR abs/2202.07721 (2022) - [i6]Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ALICE: An Automatic Design Flow for eFPGA Redaction. CoRR abs/2205.07425 (2022) - 2021
- [j33]Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon:
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test 38(2): 5-7 (2021) - [j32]Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. 17(2): 24:1-24:27 (2021) - [c121]Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon:
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP 2021: 57-60 - [c120]Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC 2021: 530-535 - [c119]Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC 2021: 859-864 - [c118]Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon:
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. DAC 2021: 1331-1334 - [c117]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c116]Thomas Becnel, Pierre-Emmanuel Gaillardon:
A Deep Learning Approach to Sensor Fusion Inference at the Edge. DATE 2021: 1420-1425 - [c115]Xifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon:
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. FPL 2021: 400 - [c114]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. ICCAD 2021: 1-9 - [c113]Aurélien Alacchi, Edouard Giacomin, Xifan Tang, Pierre-Emmanuel Gaillardon:
Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. ISCAS 2021: 1-5 - [c112]Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. ISCAS 2021: 1-5 - [c111]Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. ISPD 2021: 135-142 - [c110]Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. VLSI-SoC 2021: 1-6 - [c109]Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. VLSI-SoC 2021: 1-6 - [c108]Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. VLSI-SoC (Selected Papers) 2021: 205-224 - [e2]Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis:
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 621, Springer 2021, ISBN 978-3-030-81640-7 [contents] - [i5]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. CoRR abs/2110.13346 (2021) - [i4]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction. CoRR abs/2111.04222 (2021) - [i3]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR abs/2112.00621 (2021) - 2020
- [j31]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8: 226828-226844 (2020) - [j30]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020) - [j29]Xifan Tang, Edouard Giacomin, Baudouin Chauviere, Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. IEEE Micro 40(4): 41-48 (2020) - [c107]Xifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon:
A RRAM-based FPGA for Energy-efficient Edge Computing. DATE 2020: 144- - [c106]Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE 2020: 670-673 - [c105]Mohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael T. Niemier, Xiaobo Sharon Hu:
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks. DATE 2020: 1253-1258 - [c104]Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA 2020: 349-362 - [c103]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC 2020: 34-39 - [c102]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) 2020: 279-300 - [e1]Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis:
VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 586, Springer 2020, ISBN 978-3-030-53272-7 [contents] - [i2]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j28]Thomas Becnel, Kyle Tingey, Jonathan Whitaker, Tofigh Sayahi, Katrina Lê, Pascal Goffin, Anthony Butterfield, Kerry Kelly, Pierre-Emmanuel Gaillardon:
A Distributed Low-Cost Pollution Monitoring Platform. IEEE Internet Things J. 6(6): 10738-10748 (2019) - [j27]Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon:
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 643-654 (2019) - [j26]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 637-650 (2019) - [j25]Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1486-1503 (2019) - [c101]Patsy Cadareanu, N. Reddy C, Carmen G. Almudéver, A. Khanna, Arijit Raychowdhury, Suman Datta, Koen Bertels, Vijayakrishan Narayanan, Massimiliano Di Ventra, Pierre-Emmanuel Gaillardon:
Rebooting Our Computing Models. DATE 2019: 1469-1476 - [c100]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Scalable Boolean Methods in a Modern Synthesis Flow. DATE 2019: 1643-1648 - [c99]Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon:
OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. FPL 2019: 367-374 - [c98]Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD 2019: 1-6 - [c97]Thomas Becnel, Tofigh Sayahi, Kerry Kelly, Pierre-Emmanuel Gaillardon:
A Recursive Approach to Partially Blind Calibration of a Pollution Sensor Network. ICESS 2019: 1-8 - [c96]Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. FPT 2019: 247-250 - [c95]Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon:
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI 2019: 224-229 - [c94]Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO 2019: 1-13 - [c93]Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO 2019: 334-346 - [c92]Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza:
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS 2019: 1-4 - [c91]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC 2019: 160-165 - [c90]Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC 2019: 172-177 - [c89]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) 2019: 257-278 - [c88]Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC (Selected Papers) 2019: 307-322 - [p2]Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli:
Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks 2019: 1021-1064 - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - 2018
- [j24]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 639-650 (2018) - [j23]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1422-1435 (2018) - [j22]Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing:
Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2581-2583 (2018) - [c87]Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Towards high-performance polarity-controllable FETs with 2D materials. DATE 2018: 637-641 - [c86]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - [c85]Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. DRC 2018: 1-2 - [c84]Shubham Rai, Srivatsa Rangachar Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar:
Emerging reconfigurable nanotechnologies: can they support future electronics? ICCAD 2018: 13 - [c83]Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon:
An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors. ICRC 2018: 1-8 - [c82]Edouard Giacomin, Pierre-Emmanuel Gaillardon:
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. VLSI-SoC 2018: 107-112 - 2017
- [j21]Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli:
A PLiM Computer for the Internet of Things. Computer 50(6): 35-40 (2017) - [j20]Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Exact Synthesis of Majority-Inverter Graphs and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1842-1855 (2017) - [j19]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1173-1186 (2017) - [j18]Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers. IEEE Trans. Emerg. Top. Comput. 5(2): 210-222 (2017) - [c81]Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A novel basis for logic rewriting. ASP-DAC 2017: 151-156 - [c80]Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Multi-level logic benchmarks: An exactness study. ASP-DAC 2017: 157-162 - [c79]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. DATE 2017: 1092-1097 - [c78]Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins:
Wave pipelining for majority-based beyond-CMOS technologies. DATE 2017: 1306-1311 - [c77]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - [c76]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - [c75]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - [c74]Sebastien Naus, Ioulia Tzouvadaki, Pierre-Emmanuel Gaillardon, Armando Biscontini, Giovanni De Micheli, Sandro Carrara:
An efficient electronic measurement interface for memristive biosensors. ISCAS 2017: 1-4 - [c73]Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
RM3 based logic synthesis (Special session paper). ISCAS 2017: 1-4 - [c72]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Physical Design Considerations of One-level RRAM-based Routing Multiplexers. ISPD 2017: 47-54 - [c71]Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Optimization opportunities in RRAM-based FPGA architectures. LASCAS 2017: 1-4 - [c70]Edouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon:
Low-power multiplexer designs using three-independent-gate field effect transistors. NANOARCH 2017: 33-38 - [c69]John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2016
- [j17]Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici:
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 339-351 (2016) - [j16]Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Xunzhao Yin, Xiaobo Sharon Hu, Michael T. Niemier, Yier Jin:
Emerging Technology-Based Design of Primitives for Hardware Security. ACM J. Emerg. Technol. Comput. Syst. 13(1): 3:1-3:19 (2016) - [j15]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ACM J. Emerg. Technol. Comput. Syst. 13(2): 16:1-16:13 (2016) - [j14]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Anupam Chattopadhyay, Giovanni De Micheli:
A Sound and Complete Axiomatization of Majority-n Logic. IEEE Trans. Computers 65(9): 2889-2895 (2016) - [j13]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-Inverter Graph: A New Paradigm for Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 806-819 (2016) - [j12]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 1995-2007 (2016) - [j11]Xifan Tang, Gain Kim, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A Study on the Programming Structures for RRAM-Based FPGA Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(4): 503-516 (2016) - [c68]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-based synthesis for nanotechnologies. ASP-DAC 2016: 499-502 - [c67]Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli:
An MIG-based compiler for programmable logic-in-memory architectures. DAC 2016: 117:1-117:6 - [c66]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli:
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. DATE 2016: 175-180 - [c65]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli:
The Programmable Logic-in-Memory (PLiM) computer. DATE 2016: 427-432 - [c64]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE 2016: 948-953 - [c63]Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Optimizing Majority-Inverter Graphs with functional hashing. DATE 2016: 1030-1035 - [c62]Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). FPGA 2016: 281 - [c61]Pierre-Emmanuel Gaillardon, Mehdi Hasan, Anirban Saha, Luca Gaetano Amarù, Ross Walker, Berardi Sensale Rodriguez:
Digital, analog and RF design opportunities of three-independent-gate transistors. ISCAS 2016: 405-408 - [c60]Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Notes on Majority Boolean Algebra. ISMVL 2016: 50-55 - [c59]Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné:
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. LATS 2016: 195-200 - [c58]Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Inversion optimization in Majority-Inverter Graphs. NANOARCH 2016: 15-20 - 2015
- [j10]Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli:
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. ACM J. Emerg. Technol. Comput. Syst. 12(2): 12:1-12:26 (2015) - [j9]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli:
New Logic Synthesis as Nanotechnology Enabler. Proc. IEEE 103(11): 2168-2195 (2015) - [j8]Pierre-Emmanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli:
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2187-2197 (2015) - [c57]Luca Gaetano Amarù, Gage Hills, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli:
Multiple Independent Gate FETs: How many gates do we need? ASP-DAC 2015: 243-248 - [c56]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Fault modeling in controllable polarity silicon nanowire circuits. DATE 2015: 453-458 - [c55]Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
A ultra-low-power FPGA based on monolithically integrated RRAMs. DATE 2015: 1203-1208 - [c54]Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A surface potential and current model for polarity-controllable silicon nanowire FETs. ESSDERC 2015: 48-51 - [c53]Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amarù, Giovanni De Micheli:
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). FPGA 2015: 262 - [c52]Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Accurate power analysis for near-Vt RRAM-based FPGA. FPL 2015: 1-4 - [c51]Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI 2015: 39-44 - [c50]Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael T. Niemier, Xiaobo Sharon Hu:
Reliable and high performance STT-MRAM architectures based on controllable-polarity devices. ICCD 2015: 343-350 - [c49]Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
FPGA-SPICE: A simulation-based power estimation framework for FPGAs. ICCD 2015: 696-703 - [c48]Anupam Chattopadhyay, Alessandro Littarru, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Reversible Logic Synthesis via Biconditional Binary Decision Diagrams. ISMVL 2015: 2-7 - [c47]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli:
Exploiting Circuit Duality to Speed up SAT. ISVLSI 2015: 101-106 - [c46]Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. ISVLSI 2015: 491-496 - [c45]Johan Broc, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jaume Joven Murillo, Krishna V. Palem, Giovanni De Micheli:
A fast pruning technique for low-power inexact Circuit design. LASCAS 2015: 1-4 - [c44]Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A study on buffer distribution for RRAM-based FPGA routing structures. LASCAS 2015: 1-4 - [c43]Winston Haaswijk, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
NEM relay design with biconditional binary decision diagrams. NANOARCH 2015: 45-50 - [i1]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Anupam Chattopadhyay, Giovanni De Micheli:
A Sound and Complete Axiomatization of Majority-n Logic. CoRR abs/1502.06359 (2015) - 2014
- [j7]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 487-500 (2014) - [j6]Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli:
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. 10(4): 33:1-33:19 (2014) - [j5]Jian Zhang, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2851-2861 (2014) - [j4]Ibrahim Kazi, Pascal Andreas Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Yusuf Leblebici, Andreas Peter Burg, Giovanni De Micheli:
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3155-3164 (2014) - [c42]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli:
Data compression via logic synthesis. ASP-DAC 2014: 628-633 - [c41]Yu Bi, Pierre-Emmanuel Gaillardon, Xiaobo Sharon Hu, Michael T. Niemier, Jiann-Shiun Yuan, Yier Jin:
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs. ATS 2014: 342-347 - [c40]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. DAC 2014: 194:1-194:6 - [c39]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
An efficient manipulation package for Biconditional Binary Decision Diagrams. DATE 2014: 1-6 - [c38]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Jian Zhang, Giovanni De Micheli:
Advanced system on a chip design based on controllable-polarity FETs. DATE 2014: 1-6 - [c37]Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli:
Majority Logic Synthesis for Spin Wave Technology. DSD 2014: 691-694 - [c36]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli:
A new basic logic structure for data-path computation (abstract only). FPGA 2014: 241 - [c35]Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Pattern-based FPGA logic block and clustering algorithm. FPL 2014: 1-4 - [c34]Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A high-performance low-power near-Vt RRAM-based FPGA. FPT 2014: 207-214 - [c33]Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements. ISCAS 2014: 1416-1419 - [c32]Xifan Tang, Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs. ISCAS 2014: 1660-1663 - [c31]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli:
Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. ISVLSI 2014: 403-405 - [c30]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli:
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. NANOARCH 2014: 163-168 - [c29]Fabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon:
3D technologies for reconfigurable architectures. ReCoSoC 2014: 1-2 - [c28]Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli:
Novel configurable logic block architecture exploiting controllable-polarity transistors. ReCoSoC 2014: 1-3 - 2013
- [j3]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli:
Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 672-676 (2013) - [c27]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. ASP-DAC 2013: 133-138 - [c26]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. DAC 2013: 47:1-47:6 - [c25]Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Towards structured ASICs using polarity-tunable Si nanowire transistors. DAC 2013: 123:1-123:4 - [c24]Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. DATE 2013: 625-630 - [c23]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. DATE 2013: 1014-1017 - [c22]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli:
A fast TCAD-based methodology for Variation analysis of emerging nano-devices. DFTS 2013: 83-88 - [c21]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli:
3.5-D integration: A case study. ISCAS 2013: 2087-2090 - [c20]Jian Zhang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs. ISCAS 2013: 2111-2114 - [c19]Ogun Turkyilmaz, Fabien Clermidy, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET. ISCAS 2013: 2127-2130 - [c18]Pierre-Emmanuel Gaillardon, Hassan Ghasemzadeh, Giovanni De Micheli:
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. LATW 2013: 1-6 - [c17]Catherine Gasnier, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT. NANOARCH 2013: 46-51 - [c16]Luca Arnani, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Efficient arithmetic logic gates using double-gate silicon nanowire FETs. NEWCAS 2013: 1-4 - [c15]Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli:
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write. NEWCAS 2013: 1-4 - 2012
- [j2]Perrine Batude, Thomas Ernst, Julien Arcamone, Gregory Arndt, Perceval Coudrain, Pierre-Emmanuel Gaillardon:
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(4): 714-722 (2012) - [c14]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH 2012: 55-60 - [c13]Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli:
GMS: Generic memristive structure for non-volatile FPGAs. VLSI-SoC 2012: 94-98 - 2011
- [j1]Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu, Maimouna Amadou, Gabriela Nicolescu:
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method. ACM J. Emerg. Technol. Comput. Syst. 7(1): 3:1-3:23 (2011) - [c12]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Paul-Henry Morel, Jean-Philippe Noël, Fabien Clermidy, Ian O'Connor:
Can we go towards true 3-D architectures? DAC 2011: 282-283 - [c11]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor:
Evaluation of a crossbar multiplexer in a lithography-based nanowire technology. ISCAS 2011: 2930-2933 - [c10]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy, Ian O'Connor:
Ultra-fine grain FPGAs: A granularity study. NANOARCH 2011: 9-15 - [c9]Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller:
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. NANOARCH 2011: 65-69 - 2010
- [c8]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi, Fabien Clermidy, Luca Perniola, Ian O'Connor:
Phase-change-memory-based storage elements for configurable logic. FPT 2010: 17-20 - [c7]Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola:
Emerging memory technologies for reconfigurable routing in FPGA architecture. ICECS 2010: 62-65 - [c6]Ian O'Connor, Kotb Jabeur, David Navarro, Nataliya Yakymets, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy:
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics. ICECS 2010: 66-69 - [c5]Kotb Jabeur, David Navarro, Ian O'Connor, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy:
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. NANOARCH 2010: 47-52
2000 – 2009
- 2009
- [c4]Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Renaud Daviot:
Reconfigurable nanoscale logic cells : a comparison study. ICECS 2009: 483-486 - [c3]Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu, Renaud Daviot:
Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme. ICECS 2009: 888-891 - [c2]Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu:
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices. NANOARCH 2009: 69-74 - [c1]Ian O'Connor, Junchen Liu, Kotb Jabeur, Nataliya Yakymets, Renaud Daviot, David Navarro, Pierre-Emmanuel Gaillardon, Fabien Clermidy, Maimouna Amadou, Gabriela Nicolescu:
Emerging Technologies and Nanoscale Computing Fabrics. VLSI-SoC 2009: 1-20
Coauthor Index
Luca G. Amarù
aka: Luca Gaetano Amarù
aka: Luca Gaetano Amarù
[j31] [e1] [j26] [j25] [c100] [p2] [j24] [c87] [c85] [j21] [j20] [j19] [j18] [c81] [c80] [c79] [c78] [c77] [c76] [c74] [c73] [c72] [c71] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [c68] [c67] [c66] [c65] [c63] [c62] [c60] [c58] [j10] [j9] [j8] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [i1] [j7] [j6] [j5] [j4] [c42] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c28] [j3] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13]
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